From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E14FDC31E50 for ; Sun, 16 Jun 2019 17:47:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 972D820866 for ; Sun, 16 Jun 2019 17:47:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="sZSXQ40i" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727200AbfFPRrq (ORCPT ); Sun, 16 Jun 2019 13:47:46 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:33362 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726121AbfFPRrp (ORCPT ); Sun, 16 Jun 2019 13:47:45 -0400 Received: by mail-wm1-f65.google.com with SMTP id h19so2904193wme.0 for ; Sun, 16 Jun 2019 10:47:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:openpgp:autocrypt:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=k32GHXPQOSojycs+3f1EfADUcN8SPLsNXB1pAx3700A=; b=sZSXQ40il31HHkyUY7WfPrQ7A+Inu3+pL1PjJ+s8M4b64bquu2O5Xczr17R5UXUvUm keuqbIAe+ZjxGaA6AHzWuPhr7GEGzBOouYg2RE6pa6LJAShUc+zjo8ObdqsL+Nhgggon Ysw+1pq9ZEH97fggUQAvgga0fxc1p0gIp+Our0fNJ3nXfUrdCvjm+N90uYrpVVuFqrjr UYD/XPMdKTituDG0Zp+udUAskJPCDA5j9E8jmEdk+RFNbf1RFO+WoOzSjvQqEoTE2k6Y zoKfJR3L108H+5TgB8wZ45srKfZQnI55tFoiZ23S/JCEPiYYqx8+Qv4VjV6v//La3hFh x98w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:openpgp:autocrypt :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=k32GHXPQOSojycs+3f1EfADUcN8SPLsNXB1pAx3700A=; b=IOuyZP39KNgljx+9m2Tg58lL+hI0zqjUdLz0i9D9u+Xq4nr5k6/h0DOrbPH9PGVNHr qnUTaL599mnqw7gIGgToSN4FyMM/GAnI2kHG4dFnEOv3QdmzYRAOkSUrJjuE2t1XjQkC 4i44j6oZ06YvyyLTmSDmQFW5CPy2B9yAbrLZBHwa/jiGJc3nSuiTF+X9SfCt8E2quGDw OngCEGjjajdx3fFlbadGGbmw9YCo0V1AcrpBIbndQibCWr2eEkmEuh8LWyv8ObGjoaHk sVm5rVGOZSay/wL23KAprXUgQEYUXr+lacTwihpUo9NpmWaL4AyFeOoC20A1d1cmFIVp zNyw== X-Gm-Message-State: APjAAAXVpY+uKhhu2L35RFE7n/KZizR0TJzfiRCZsCjnKHlugozpbxHV 2tNiAYokHyVMNb1l5meK6MZUp047VMA= X-Google-Smtp-Source: APXvYqzUqWaPTHh0BJXtzSYmaLlaxeU16DnJpdyLhtS63jKadI3LwAnHD8/A6Z+pcYq2Y/Vn3NOMpw== X-Received: by 2002:a1c:2e0a:: with SMTP id u10mr16672537wmu.92.1560707261532; Sun, 16 Jun 2019 10:47:41 -0700 (PDT) Received: from [192.168.0.41] (44.64.130.77.rev.sfr.net. [77.130.64.44]) by smtp.googlemail.com with ESMTPSA id o126sm4060798wmo.1.2019.06.16.10.47.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 16 Jun 2019 10:47:40 -0700 (PDT) Subject: Re: [PATCH 1/2] arm64: dts: rockchip: Fix multiple thermal zones conflict in rk3399.dtsi To: Krzysztof Kozlowski Cc: Robin Murphy , Heiko Stuebner , linux-kernel@vger.kernel.org, edubezval@gmail.com, manivannan.sadhasivam@linaro.org, Rob Herring , Mark Rutland , Matthias Brugger , Philipp Tomsich , Christoph Muellner , Viresh Kumar , Enric Balletbo i Serra , Emil Renner Berthing , Randy Li , Tony Xie , Vicente Bergas , Klaus Goger , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/Rockchip SoC support" , "open list:ARM/Rockchip SoC support" , dianders@chromium.org, Kukjin Kim References: <20190604165802.7338-1-daniel.lezcano@linaro.org> <5188064.YWmxIpmbGp@phil> <55b9018e-672e-522b-d0a0-c5655be0f353@linaro.org> <9bf85c22-f1ba-3dbc-0b67-17e124484fa1@linaro.org> <20190616093127.GC3826@kozik-lap> From: Daniel Lezcano Openpgp: preference=signencrypt Autocrypt: addr=daniel.lezcano@linaro.org; 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Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20190616093127.GC3826@kozik-lap> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16/06/2019 11:31, Krzysztof Kozlowski wrote: > On Fri, Jun 14, 2019 at 04:30:13PM +0200, Daniel Lezcano wrote: >> On 14/06/2019 16:02, Robin Murphy wrote: >>> On 14/06/2019 14:03, Daniel Lezcano wrote: >>>> On 14/06/2019 11:35, Heiko Stuebner wrote: >>>>> Hi Daniel, >>>>> >>>>> Am Dienstag, 4. Juni 2019, 18:57:57 CEST schrieb Daniel Lezcano: >>>>>> Currently the common thermal zones definitions for the rk3399 assumes >>>>>> multiple thermal zones are supported by the governors. This is not the >>>>>> case and each thermal zone has its own governor instance acting >>>>>> individually without collaboration with other governors. >>>>>> >>>>>> As the cooling device for the CPU and the GPU thermal zones is the >>>>>> same, each governors take different decisions for the same cooling >>>>>> device leading to conflicting instructions and an erratic behavior. >>>>>> >>>>>> As the cooling-maps is about to become an optional property, let's >>>>>> remove the cpu cooling device map from the GPU thermal zone. >>>>>> >>>>>> Signed-off-by: Daniel Lezcano >>>>>> --- >>>>>>   arch/arm64/boot/dts/rockchip/rk3399.dtsi | 9 --------- >>>>>>   1 file changed, 9 deletions(-) >>>>>> >>>>>> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi >>>>>> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi >>>>>> index 196ac9b78076..e1357e0f60f7 100644 >>>>>> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi >>>>>> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi >>>>>> @@ -821,15 +821,6 @@ >>>>>>                       type = "critical"; >>>>>>                   }; >>>>>>               }; >>>>>> - >>>>>> -            cooling-maps { >>>>>> -                map0 { >>>>>> -                    trip = <&gpu_alert0>; >>>>>> -                    cooling-device = >>>>>> -                        <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>>> -                        <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>>>> -                }; >>>>>> -            }; >>>>>>           }; >>>>>>       }; >>>>> >>>>> my knowledge of the thermal framework is not that big, but what about >>>>> the >>>>> rk3399-devices which further detail the cooling-maps like >>>>> rk3399-gru-kevin >>>>> and the rk3399-nanopc-t4 with its fan-handling in the cooling-maps? >>>> >>>> The rk3399-gru-kevin is correct. >>>> >>>> The rk3399-nanopc-t4 is not correct because the cpu and the gpu are >>>> sharing the same cooling device (the fan). There are different >>>> configurations: >>>> >>>> 1. The cpu cooling device for the CPU and the fan for the GPU >>>> >>>> 2. Different trip points on the CPU thermal zone, eg. one to for the CPU >>>> cooling device and another one for the fan. >>>> >>>> There are some variant for the above. If this board is not on battery, >>>> you may want to give priority to the throughput, so activate the fan >>>> first and then cool down the CPU. Or if you are on battery, you may want >>>> to invert the trip points. >>>> >>>> In any case, it is not possible to share the same cooling device for >>>> different thermal zones. >>> >>> OK, thanks for the clarification. I'll get my board set up again to >>> figure out the best fix for rk3399-nanopc-t4 (FWIW most users are >>> probably just using passive cooling or a plain DC fan anyway). You might >>> want to raise this issue with the maintainers of >>> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi, since the >>> everything-shared-by-everything approach in there was what I used as a >>> reference. >> >> Cc'ed: Kukjin Kim and Krzysztof Kozlowski >> >> Easy :) >> > > Assuming that all trip-points are the same between thermal zones, I > understand that solution could be to have one thermal zone with thermal > multiple sensors (some time ago bindings did not support it) and all > cooling devices? Then only one governor would be assigned? The multiple sensors, multiple thermal zones and governors dealing with different group of them is not implemented [yet]. Basically, you can consider there is a 1:1 relationship between each of them. one thermal zone = one sensor = one cooling device Given the configuration and the hardware, it would make sense to create one thermal zone per cluster. There is one clock line per cluster. It is possible to create two CPU cooling devices, one for each cluster. IMO, the fan definition is correct except it should be assigned to one thermal zone only. One configuration could be: thermal-zones { little-thermal-zone: little-thermal-zone { thermal-sensors = <&tmu_cpu0 0>; polling-delay-passive = <250>; polling-delay = <0>; trips { ltz_alert0: ltz-alert-0 { temperature = <50000>; hysteresis = <5000>; type = "active"; }; ltz_alert1: cpu-alert-1 { temperature = <60000>; hysteresis = <5000>; type = "active"; }; ltz_alert2: ltz-alert-2 { temperature = <70000>; hysteresis = <5000>; type = "active"; }; ltz_alert3: ltz-alert-3 { temperature = <75000>; hysteresis = <10000>; type = "passive"; }; ltz_crit0: ltz-crit-0 { temperature = <120000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <<z_alert0>; cooling-device = <&fan0 0 1>; }; map1 { trip = <<z_alert1>; cooling-device = <&fan0 1 2>; }; map2 { trip = <<z_alert2>; cooling-device = <&fan0 2 3>; }; map3 { trip = <<z_alert3>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, }; }; }; big-thermal-zone: big-thermal-zone { /* The same as little, except the sensor and the cpu cooling &cpu4, &cpu5, &cpu6, &cpu7 */ }; }; That said, the idle injection cooling device is for the moment being developed and that would be a good opportunity to test a real per cpu cooling device as the exynos5422 has a per core sensor. -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog