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Fri, 6 Feb 2026 05:44:25 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: AdHIckEZVcNF Date: Fri, 06 Feb 2026 11:44:04 +0100 From: "Arnd Bergmann" To: "Yushan Wang" , "Jonathan Cameron" , "Linus Walleij" Cc: "Alexandre Belloni" , "Drew Fustini" , "Krzysztof Kozlowski" , "Linus Walleij" , "Will Deacon" , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, fanghao11@huawei.com, linuxarm@huawei.com, liuyonglong@huawei.com, prime.zeng@hisilicon.com, "Zhou Wang" , "Wei Xu" , linux-mm@vger.kernel.org, "SeongJae Park" Message-Id: <55e3766e-e292-4136-9e8f-2098ffd53b5d@app.fastmail.com> In-Reply-To: <4c5eaf8f-2433-4971-b5d0-4f35acb2820e@huawei.com> References: <20260203161843.649417-1-wangyushan12@huawei.com> <20260203161843.649417-2-wangyushan12@huawei.com> <20260204134020.00002393@huawei.com> <4c5eaf8f-2433-4971-b5d0-4f35acb2820e@huawei.com> Subject: Re: [PATCH 1/3] soc cache: L3 cache driver for HiSilicon SoC Content-Type: text/plain Content-Transfer-Encoding: 7bit On Fri, Feb 6, 2026, at 11:07, wangyushan wrote: > > Let me try to explain the use case here. > > The idea is similar to this article: > https://www.cl.cam.ac.uk/~rnw24/papers/201708-sigcomm-diskcryptnet.pdf > > Suppose we have data on SSD that need to be transferred through network. > We have technologies like DDIO and IO stash to make data flow through > L3 cache instead of DDR to avoid the influence of DDR bandwidth. > > But if something is to be done to the data instead of merely copying, > and cores needs to participate, we'd like to make data to climb a bit > higher up through the memory hierarchy and stay there before data > processing is done. That is, correct amount of data being fetched to > L3 cache, and consumed just in time, then free L3 for next batch. > It is more of a userspace defined pipeline that utilizes capability > provided by kernel, where cache locks are allocated and freed quickly > with batches. > > In above use case, C2C latency is chosen to avoid DDR latency, precisely > which L3 cache to store the data is not required. (For this part maybe > including steering tag as the hint to choose the correct L3 is a smarter > way, like AMD SDCIAE). > > Memory management is, in many way, independent to architecture and > vendors, we might not want to take hardware specific feature into > account when kernel makes decisions of, say, swapping a page or not, > but we can control the hardware resource to lean more on a process, > like resctl. Ah, so if the main purpose here is to access the memory from devices, I wonder if this should be structured as a dma-buf driver. This would still allow you to mmap() a character device, but in addition allow passing the file descriptor to driver interfaces that take a dmabuf instead of a user memory pointer. Arnd