Re:Re: [PATCH] bus: mhi: host: Add support for Cinterion MV32-WA/MV32-WB

["Slark Xiao" <slark_xiao@163.com>]

At 2022-04-20 20:00:23, "Loic Poulain" <loic.poulain@linaro.org> wrote:
>Hi Slark,
>
>On Wed, 20 Apr 2022 at 12:28, Slark Xiao <slark_xiao@163.com> wrote:
>>
>> MV32-WA is designed based on Qualcomm SDX62, and
>> MV32-WB is designed based on QUalcomm SDX65. Both
>> products' enumeration would align with previous
>> product MV31-W.
>> Add some new items for mv32 to separate it from
>> mv31-w, in case we need to do any changes in
>> future.
>
>On the contrary, do not overly clone the structures, and re-use the
>mv31 ones if they apply. You can rename them to mv3x if you really
>want to.
>
>Regards,
>Loic
>
Hi Loic,
  Thanks for your suggestion.
   Actually, for different chip(like previous SDX24 and SDX55), they may 
have difference behavior. For example, the item of 'sideband_wake'
of SDX24 is true but the rest is false. It's hard to say SDX65 would 
align with SDX55 until now.
   Maybe I can re-use the same item '.config' for all MV3X products and separate 
them from device info(mhi_pci_dev_info). 
   Do you agree this?

>
>
>>
>> Signed-off-by: Slark Xiao <slark_xiao@163.com>
>> ---
>>  drivers/bus/mhi/host/pci_generic.c | 41 ++++++++++++++++++++++++++++++
>>  1 file changed, 41 insertions(+)
>>
>> diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c
>> index 541ced27d941..a2da40340df7 100644
>> --- a/drivers/bus/mhi/host/pci_generic.c
>> +++ b/drivers/bus/mhi/host/pci_generic.c
>> @@ -406,6 +406,41 @@ static const struct mhi_pci_dev_info mhi_mv31_info = {
>>         .mru_default = 32768,
>>  };
>>
>> +static const struct mhi_channel_config mhi_mv32_channels[] = {
>> +       MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0),
>> +       MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0),
>> +       /* MBIM Control Channel */
>> +       MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0),
>> +       MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0),
>> +       /* MBIM Data Channel */
>> +       MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2),
>> +       MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3),
>> +};
>> +
>> +static struct mhi_event_config mhi_mv32_events[] = {
>> +       MHI_EVENT_CONFIG_CTRL(0, 256),
>> +       MHI_EVENT_CONFIG_DATA(1, 256),
>> +       MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
>> +       MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101),
>> +};
>> +
>> +static const struct mhi_controller_config modem_mv32_config = {
>> +       .max_channels = 128,
>> +       .timeout_ms = 20000,
>> +       .num_channels = ARRAY_SIZE(mhi_mv32_channels),
>> +       .ch_cfg = mhi_mv32_channels,
>> +       .num_events = ARRAY_SIZE(mhi_mv32_events),
>> +       .event_cfg = mhi_mv32_events,
>> +};
>> +
>> +static const struct mhi_pci_dev_info mhi_mv32_info = {
>> +       .name = "cinterion-mv32",
>> +       .config = &modem_mv32_config,
>> +       .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
>> +       .dma_data_width = 32,
>> +       .mru_default = 32768,
>> +};
>> +
>>  static const struct mhi_channel_config mhi_sierra_em919x_channels[] = {
>>         MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0),
>>         MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 256, 0),
>> @@ -475,6 +510,12 @@ static const struct pci_device_id mhi_pci_id_table[] = {
>>         /* MV31-W (Cinterion) */
>>         { PCI_DEVICE(0x1269, 0x00b3),
>>                 .driver_data = (kernel_ulong_t) &mhi_mv31_info },
>> +       /* MV32-WA (Cinterion) */
>> +       { PCI_DEVICE(0x1269, 0x00ba),
>> +               .driver_data = (kernel_ulong_t) &mhi_mv32_info },
>> +       /* MV32-WB (Cinterion) */
>> +       { PCI_DEVICE(0x1269, 0x00bb),
>> +               .driver_data = (kernel_ulong_t) &mhi_mv32_info },
>>         {  }
>>  };
>>  MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
>> --
>> 2.25.1
>>