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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e7e8f9b4sm990861366b.11.2025.07.15.03.45.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Jul 2025 03:45:38 -0700 (PDT) Message-ID: <55f2e014-044c-4021-8b01-99bdf2a0fd7f@oss.qualcomm.com> Date: Tue, 15 Jul 2025 12:45:36 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] PCI: qcom: Move qcom_pcie_icc_opp_update() to notifier callback To: Manivannan Sadhasivam Cc: Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , Krishna Chaitanya Chundru References: <20250714-aspm_fix-v1-0-7d04b8c140c8@oss.qualcomm.com> <20250714-aspm_fix-v1-2-7d04b8c140c8@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE1MDA5OCBTYWx0ZWRfX98nkU0dLMaeX gl6hY/ry49kQbVKxA7ytwc+9T+MC3fP5mxu6GWgt+OND1Ywny3e9HBowCqt6cf/JupU6xaC+/FI mLNO4+zLPbYGp4nzxNF59EEdUg7Cls9jv+LhyLYZOsy5k1Vc/yqmW0D3E+kfQLa/HmIzHMzUkdM BJFLutviLaSne5GO4dZ1sB7lo6ZJEqkAL4TvwjJd5fUuLES8n5C043U3x2Df0aM6H1VbvWyutZy nIDftkVxHPfikCuvYxM822/vhngC9sdgE9+YB7BBLE7nL8hEKPOAYCbOh0YR6XT6hmGtdOKLm0N Jld2OID9PnwJVHwLRZ6mtfgM1w/pEtqI6oOAHYaVBtq2UFVrZKKCGzisfM97JZoW5AhY9hKh28T 5MjcjiS91hwk5u7QG2NkHLijVqoaT1dMhrcQ1SPBj6aV8sLwMf9nTsiXzksKJpmXtVEXNKWu X-Proofpoint-GUID: -xFEfyIfsC83olICZZgQgUFs7UO9eAP5 X-Authority-Analysis: v=2.4 cv=SZT3duRu c=1 sm=1 tr=0 ts=68763154 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=uNiOjgRUHSxkwL6ZQ2AA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-ORIG-GUID: -xFEfyIfsC83olICZZgQgUFs7UO9eAP5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-15_01,2025-07-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 mlxscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507150098 On 7/15/25 12:36 PM, Manivannan Sadhasivam wrote: > On Tue, Jul 15, 2025 at 11:54:48AM GMT, Konrad Dybcio wrote: >> On 7/14/25 8:01 PM, Manivannan Sadhasivam wrote: >>> It allows us to group all the settings that need to be done when a PCI >>> device is attached to the bus in a single place. >>> >>> Signed-off-by: Manivannan Sadhasivam >>> --- >>> drivers/pci/controller/dwc/pcie-qcom.c | 3 +-- >>> 1 file changed, 1 insertion(+), 2 deletions(-) >>> >>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >>> index b4993642ed90915299e825e47d282b8175a78346..b364977d78a2c659f65f0f12ce4274601d20eaa6 100644 >>> --- a/drivers/pci/controller/dwc/pcie-qcom.c >>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >>> @@ -1616,8 +1616,6 @@ static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) >>> pci_lock_rescan_remove(); >>> pci_rescan_bus(pp->bridge->bus); >>> pci_unlock_rescan_remove(); >>> - >>> - qcom_pcie_icc_opp_update(pcie); >>> } else { >>> dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", >>> status); >>> @@ -1765,6 +1763,7 @@ static int pcie_qcom_notify(struct notifier_block *nb, unsigned long action, >>> switch (action) { >>> case BUS_NOTIFY_BIND_DRIVER: >>> qcom_pcie_enable_aspm(pdev); >>> + qcom_pcie_icc_opp_update(pcie); >> >> So I assume that we're not exactly going to do much with the device if >> there isn't a driver for it, but I have concerns that since the link >> would already be established(?), the icc vote may be too low, especially >> if the user uses something funky like UIO >> > > Hmm, that's a good point. Not enabling ASPM wouldn't have much consequence, but > not updating OPP would be. > > Let me think of other ways to call these two APIs during the device addition. If > there are no sane ways, I'll drop *this* patch. Would it be too naive to assume BUS_NOTIFY_ADD_DEVICE is a good fit? Do ASPM setting need to be reapplied after the PCIe device is reset? (well I would assume there are probably multiple levels of "reset" :/) Konrad