From: Nicolas Ferre <nicolas.ferre@atmel.com>
To: Ludovic Desroches <ludovic.desroches@atmel.com>,
<tglx@linutronix.de>, <jason@lakedaemon.net>,
<marc.zyngier@arm.com>
Cc: <linux-kernel@vger.kernel.org>, <sasha.levin@oracle.com>,
<linux-arm-kernel@lists.infradead.org>,
<alexandre.belloni@free-electrons.com>,
<boris.brezillon@free-electrons.com>, <Wenyou.Yang@atmel.com>
Subject: Re: [PATCH 3/3] irqchip: atmel-aic5: simplify base chip selection
Date: Tue, 22 Sep 2015 10:27:51 +0200 [thread overview]
Message-ID: <56011107.3050705@atmel.com> (raw)
In-Reply-To: <1442843173-2390-3-git-send-email-ludovic.desroches@atmel.com>
Le 21/09/2015 15:46, Ludovic Desroches a écrit :
> Use irq_get_domain_generic_chip() to select the base chip.
>
> Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
> drivers/irqchip/irq-atmel-aic5.c | 28 ++++++++++------------------
> 1 file changed, 10 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c
> index abff79e..7264ec7 100644
> --- a/drivers/irqchip/irq-atmel-aic5.c
> +++ b/drivers/irqchip/irq-atmel-aic5.c
> @@ -70,8 +70,7 @@ static struct irq_domain *aic5_domain;
> static asmlinkage void __exception_irq_entry
> aic5_handle(struct pt_regs *regs)
> {
> - struct irq_domain_chip_generic *dgc = aic5_domain->gc;
> - struct irq_chip_generic *bgc = dgc->gc[0];
> + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(aic5_domain, 0);
> u32 irqnr;
> u32 irqstat;
>
> @@ -87,8 +86,7 @@ aic5_handle(struct pt_regs *regs)
> static void aic5_mask(struct irq_data *d)
> {
> struct irq_domain *domain = d->domain;
> - struct irq_domain_chip_generic *dgc = domain->gc;
> - struct irq_chip_generic *bgc = dgc->gc[0];
> + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
> struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
>
> /* Disable interrupt on AIC5 */
> @@ -102,8 +100,7 @@ static void aic5_mask(struct irq_data *d)
> static void aic5_unmask(struct irq_data *d)
> {
> struct irq_domain *domain = d->domain;
> - struct irq_domain_chip_generic *dgc = domain->gc;
> - struct irq_chip_generic *bgc = dgc->gc[0];
> + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
> struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
>
> /* Enable interrupt on AIC5 */
> @@ -117,8 +114,7 @@ static void aic5_unmask(struct irq_data *d)
> static int aic5_retrigger(struct irq_data *d)
> {
> struct irq_domain *domain = d->domain;
> - struct irq_domain_chip_generic *dgc = domain->gc;
> - struct irq_chip_generic *bgc = dgc->gc[0];
> + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
>
> /* Enable interrupt on AIC5 */
> irq_gc_lock(bgc);
> @@ -132,8 +128,7 @@ static int aic5_retrigger(struct irq_data *d)
> static int aic5_set_type(struct irq_data *d, unsigned type)
> {
> struct irq_domain *domain = d->domain;
> - struct irq_domain_chip_generic *dgc = domain->gc;
> - struct irq_chip_generic *bgc = dgc->gc[0];
> + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
> unsigned int smr;
> int ret;
>
> @@ -153,7 +148,7 @@ static void aic5_suspend(struct irq_data *d)
> {
> struct irq_domain *domain = d->domain;
> struct irq_domain_chip_generic *dgc = domain->gc;
> - struct irq_chip_generic *bgc = dgc->gc[0];
> + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
> struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
> int i;
> u32 mask;
> @@ -177,7 +172,7 @@ static void aic5_resume(struct irq_data *d)
> {
> struct irq_domain *domain = d->domain;
> struct irq_domain_chip_generic *dgc = domain->gc;
> - struct irq_chip_generic *bgc = dgc->gc[0];
> + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
> struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
> int i;
> u32 mask;
> @@ -201,7 +196,7 @@ static void aic5_pm_shutdown(struct irq_data *d)
> {
> struct irq_domain *domain = d->domain;
> struct irq_domain_chip_generic *dgc = domain->gc;
> - struct irq_chip_generic *bgc = dgc->gc[0];
> + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
> struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
> int i;
>
> @@ -256,12 +251,11 @@ static int aic5_irq_domain_xlate(struct irq_domain *d,
> irq_hw_number_t *out_hwirq,
> unsigned int *out_type)
> {
> - struct irq_domain_chip_generic *dgc = d->gc;
> - struct irq_chip_generic *bgc;
> + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(d, 0);
> unsigned smr;
> int ret;
>
> - if (!dgc)
> + if (!bgc)
> return -EINVAL;
>
> ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
> @@ -269,8 +263,6 @@ static int aic5_irq_domain_xlate(struct irq_domain *d,
> if (ret)
> return ret;
>
> - bgc = dgc->gc[0];
> -
> irq_gc_lock(bgc);
> irq_reg_writel(bgc, *out_hwirq, AT91_AIC5_SSR);
> smr = irq_reg_readl(bgc, AT91_AIC5_SMR);
>
--
Nicolas Ferre
next prev parent reply other threads:[~2015-09-22 8:28 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-21 13:46 [PATCH 1/3] irqchip: atmel-aic5: fix bug with mask/unmask Ludovic Desroches
2015-09-21 13:46 ` [PATCH 2/3] irqchip: atmel-aic5: fix variable naming Ludovic Desroches
2015-09-22 8:27 ` Nicolas Ferre
2015-09-22 14:09 ` [tip:irq/core] irqchip/atmel-aic5: Use explicit variable name for the base chip tip-bot for Ludovic Desroches
2015-09-21 13:46 ` [PATCH 3/3] irqchip: atmel-aic5: simplify base chip selection Ludovic Desroches
2015-09-22 8:27 ` Nicolas Ferre [this message]
2015-09-22 14:09 ` [tip:irq/core] irqchip/atmel-aic5: Simplify " tip-bot for Ludovic Desroches
2015-09-22 7:45 ` [PATCH 1/3] irqchip: atmel-aic5: fix bug with mask/unmask Boris Brezillon
2015-09-22 8:27 ` Nicolas Ferre
2015-09-22 10:27 ` Thomas Gleixner
2015-09-22 11:55 ` Boris Brezillon
2015-09-22 13:50 ` Thomas Gleixner
2015-09-22 14:07 ` Ludovic Desroches
2015-09-22 10:30 ` [tip:irq/urgent] irqchip/atmel-aic5: Use proper mask cache in mask/unmask() tip-bot for Ludovic Desroches
2015-09-22 10:37 ` Thomas Gleixner
2015-09-22 14:00 ` [tip:irq/urgent] irqchip/atmel-aic5: Use per chip mask caches " tip-bot for Ludovic Desroches
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=56011107.3050705@atmel.com \
--to=nicolas.ferre@atmel.com \
--cc=Wenyou.Yang@atmel.com \
--cc=alexandre.belloni@free-electrons.com \
--cc=boris.brezillon@free-electrons.com \
--cc=jason@lakedaemon.net \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=ludovic.desroches@atmel.com \
--cc=marc.zyngier@arm.com \
--cc=sasha.levin@oracle.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
Powered by JetHome