From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751546AbbJMShc (ORCPT ); Tue, 13 Oct 2015 14:37:32 -0400 Received: from smtp-outbound-1.vmware.com ([208.91.2.12]:49700 "EHLO smtp-outbound-1.vmware.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751039AbbJMShb convert rfc822-to-8bit (ORCPT ); Tue, 13 Oct 2015 14:37:31 -0400 Subject: Re: [PATCH] drm/vmwgfx: switch from ioremap_cache to memremap To: Dan Williams References: <20151012223527.34143.87313.stgit@dwillia2-desk3.jf.intel.com> <561C9427.8020001@vmware.com> CC: David Airlie , "linux-kernel@vger.kernel.org" , , Sinclair Yeh From: Thomas Hellstrom X-Enigmail-Draft-Status: N1110 Message-ID: <561D4F65.5080908@vmware.com> Date: Tue, 13 Oct 2015 20:37:25 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT X-Originating-IP: [10.113.160.246] X-ClientProxiedBy: EX13-CAS-013.vmware.com (10.113.191.65) To EX13-MBX-024.vmware.com (10.113.191.44) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/13/2015 06:35 PM, Dan Williams wrote: > On Mon, Oct 12, 2015 at 10:18 PM, Thomas Hellstrom > wrote: >> Hi! >> >> On 10/13/2015 12:35 AM, Dan Williams wrote: >>> Per commit 2e586a7e017a "drm/vmwgfx: Map the fifo as cached" the driver >>> expects the fifo registers to be cacheable. In preparation for >>> deprecating ioremap_cache() convert its usage in vmwgfx to memremap(). >>> >>> Cc: David Airlie >>> Cc: Thomas Hellstrom >>> Cc: Sinclair Yeh >>> Cc: dri-devel@lists.freedesktop.org >>> Signed-off-by: Dan Williams >> While I have nothing against the conversion, what's stopping the >> compiler from reordering writes on a generic architecture and caching >> and reordering reads on x86 in particular? At the very least it looks to >> me like the memory accesses of the memremap'd memory needs to be >> encapsulated within READ_ONCE and WRITE_ONCE. > Hmm, currently the code is using ioread32/iowrite32 which only do > volatile accesses, whereas READ_ONCE / WRITE_ONCE have a memory > clobber on entry and exit. So, I'm assuming all you need is the > guarantee of "no compiler re-ordering" and not the stronger > READ_ONCE/WRITE_ONCE guarantees, but that still seems broken compared > to explicit fencing where it matters. I'm not quite sure I follow you here, it looks to me like READ_ONCE() and WRITE_ONCE() are implemented as volatile accesses, http://lxr.free-electrons.com/source/include/linux/compiler.h#L215 just like ioread32 and iowrite32 http://lxr.free-electrons.com/source/include/asm-generic/io.h#L54 which would minimize any potential impact of this change. IMO optimizing the memory accesses can be done as a later step. /Thomas