From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753793AbbJNN0o (ORCPT ); Wed, 14 Oct 2015 09:26:44 -0400 Received: from mail-wi0-f175.google.com ([209.85.212.175]:36441 "EHLO mail-wi0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753297AbbJNN0m (ORCPT ); Wed, 14 Oct 2015 09:26:42 -0400 Subject: Re: [PATCH v7 9/9] arm64: dts: mt8173: Add subsystem clock controller device nodes To: James Liao , Mike Turquette , Stephen Boyd , Heiko Stubner References: <1439200228-318-1-git-send-email-jamesjj.liao@mediatek.com> <1439200228-318-10-git-send-email-jamesjj.liao@mediatek.com> Cc: srv_heupstream@mediatek.com, Daniel Kurtz , Ricky Liang , Rob Herring , Sascha Hauer , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org From: Matthias Brugger Message-ID: <561E580D.4090706@gmail.com> Date: Wed, 14 Oct 2015 15:26:37 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <1439200228-318-10-git-send-email-jamesjj.liao@mediatek.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/08/15 11:50, James Liao wrote: > This patch adds device nodes providing subsystem clocks on MT8173, > includes mmsys, imgsys, vdecsys, vencsys and vencltsys. > > Signed-off-by: James Liao > --- Applied, thanks. > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 37 ++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > index a2f63e4..32c85cc 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > @@ -102,6 +102,13 @@ > clock-output-names = "clk32k"; > }; > > + cpum_ck: oscillator@2 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <0>; > + clock-output-names = "cpum_ck"; > + }; > + > timer { > compatible = "arm,armv8-timer"; > interrupt-parent = <&gic>; > @@ -227,6 +234,36 @@ > clocks = <&uart_clk>; > status = "disabled"; > }; > + > + mmsys: clock-controller@14000000 { > + compatible = "mediatek,mt8173-mmsys", "syscon"; > + reg = <0 0x14000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + imgsys: clock-controller@15000000 { > + compatible = "mediatek,mt8173-imgsys", "syscon"; > + reg = <0 0x15000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vdecsys: clock-controller@16000000 { > + compatible = "mediatek,mt8173-vdecsys", "syscon"; > + reg = <0 0x16000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vencsys: clock-controller@18000000 { > + compatible = "mediatek,mt8173-vencsys", "syscon"; > + reg = <0 0x18000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vencltsys: clock-controller@19000000 { > + compatible = "mediatek,mt8173-vencltsys", "syscon"; > + reg = <0 0x19000000 0 0x1000>; > + #clock-cells = <1>; > + }; > }; > }; > >