From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752191AbbJRWe0 (ORCPT ); Sun, 18 Oct 2015 18:34:26 -0400 Received: from hauke-m.de ([5.39.93.123]:45532 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751482AbbJRWeY (ORCPT ); Sun, 18 Oct 2015 18:34:24 -0400 Subject: Re: [RFC 3/5] ARM: dts: enable clock support for BCM5301X To: Jon Mason , Michael Turquette , Stephen Boyd References: <1444771347-11382-1-git-send-email-jonmason@broadcom.com> <1444771347-11382-4-git-send-email-jonmason@broadcom.com> Cc: Florian Fainelli , Ray Jui , Scott Branden , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com From: Hauke Mehrtens Message-ID: <56241E6A.2060406@hauke-m.de> Date: Mon, 19 Oct 2015 00:34:18 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <1444771347-11382-4-git-send-email-jonmason@broadcom.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/13/2015 11:22 PM, Jon Mason wrote: > Replace current device tree dummy clocks with real clock support for > Broadcom Northstar SoCs. > > Signed-off-by: Jon Mason The clock-frequency of the uarts should also be replaced with the correct clock from the clock driver. Hauke > --- > arch/arm/boot/dts/bcm5301x.dtsi | 88 ++++++++++++++++++++++++++++++++--------- > 1 file changed, 69 insertions(+), 19 deletions(-) > > diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi > index 6f50f67..1eca551 100644 > --- a/arch/arm/boot/dts/bcm5301x.dtsi > +++ b/arch/arm/boot/dts/bcm5301x.dtsi > @@ -8,6 +8,7 @@ > * Licensed under the GNU/GPL. See COPYING for details. > */ > > +#include > #include > #include > #include > @@ -42,41 +43,48 @@ > > mpcore { > compatible = "simple-bus"; > - ranges = <0x00000000 0x19020000 0x00003000>; > + ranges = <0x00000000 0x19000000 0x00023000>; > #address-cells = <1>; > #size-cells = <1>; > > - scu@0000 { > + a9pll: arm_clk@00000 { > + #clock-cells = <0>; > + compatible = "brcm,nsp-armpll"; > + clocks = <&osc>; > + reg = <0x00000 0x1000>; > + }; > + > + scu@20000 { > compatible = "arm,cortex-a9-scu"; > - reg = <0x0000 0x100>; > + reg = <0x20000 0x100>; > }; > > - timer@0200 { > + timer@20200 { > compatible = "arm,cortex-a9-global-timer"; > - reg = <0x0200 0x100>; > + reg = <0x20200 0x100>; > interrupts = ; > - clocks = <&clk_periph>; > + clocks = <&periph_clk>; > }; > > - local-timer@0600 { > + local-timer@20600 { > compatible = "arm,cortex-a9-twd-timer"; > - reg = <0x0600 0x100>; > + reg = <0x20600 0x100>; > interrupts = ; > - clocks = <&clk_periph>; > + clocks = <&periph_clk>; > }; > > - gic: interrupt-controller@1000 { > + gic: interrupt-controller@21000 { > compatible = "arm,cortex-a9-gic"; > #interrupt-cells = <3>; > #address-cells = <0>; > interrupt-controller; > - reg = <0x1000 0x1000>, > - <0x0100 0x100>; > + reg = <0x21000 0x1000>, > + <0x20100 0x100>; > }; > > - L2: cache-controller@2000 { > + L2: cache-controller@22000 { > compatible = "arm,pl310-cache"; > - reg = <0x2000 0x1000>; > + reg = <0x22000 0x1000>; > cache-unified; > arm,shared-override; > prefetch-data = <1>; > @@ -94,14 +102,37 @@ > > clocks { > #address-cells = <1>; > - #size-cells = <0>; > + #size-cells = <1>; > + ranges; > > - /* As long as we do not have a real clock driver us this > - * fixed clock */ > - clk_periph: periph { > + osc: oscillator { > + #clock-cells = <0>; > compatible = "fixed-clock"; > + clock-frequency = <25000000>; > + }; > + > + iprocmed: iprocmed { > + #clock-cells = <0>; > + compatible = "fixed-factor-clock"; > + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; > + clock-div = <2>; > + clock-mult = <1>; > + }; > + > + iprocslow: iprocslow { > + #clock-cells = <0>; > + compatible = "fixed-factor-clock"; > + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; > + clock-div = <4>; > + clock-mult = <1>; > + }; > + > + periph_clk: periph_clk { > #clock-cells = <0>; > - clock-frequency = <400000000>; > + compatible = "fixed-factor-clock"; > + clocks = <&a9pll>; > + clock-div = <2>; > + clock-mult = <1>; > }; > }; > > @@ -178,6 +209,25 @@ > }; > }; > > + lcpll0: lcpll0@1800c100 { > + #clock-cells = <1>; > + compatible = "brcm,nsp-lcpll0"; > + reg = <0x1800c100 0x14>; > + clocks = <&osc>; > + clock-output-names = "lcpll0", "pcie_phy", "sdio", > + "ddr_phy"; > + }; > + > + genpll: genpll@1800c140 { > + #clock-cells = <1>; > + compatible = "brcm,nsp-genpll"; > + reg = <0x1800c140 0x24>; > + clocks = <&osc>; > + clock-output-names = "genpll", "phy", "ethernetclk", > + "usbclk", "iprocfast", "sata1", > + "sata2"; > + }; > + > nand: nand@18028000 { > compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; > reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; >