From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EAF44221FC0; Fri, 20 Jun 2025 12:33:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750422799; cv=none; b=foTglVF0mf2kJxXhM273WlaEIsNnP5DjiiLeNoUWwNAI3whNsw5nMMxF4JUdVT+JOJA7sHl9pDKX8lgeg/N4sb4i7KnmjNsxOy/IX/WALoKus8U7wU3210Vg4o0Q823wPCT3R7xD9quFgHL6WNUo6ayvVdCHtpvdtNRuIxNnP88= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750422799; c=relaxed/simple; bh=8lXtsibUqhfDv7u5UfJVjn6rzJDXDt2W0ozpaZZ+90A=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=lcTNtZ1K2w6s40YdLsS3fsotuJHmgC40FIuVSq2ESCbd3kI880uXku9woFh7FC3BVZe7gFna8IzkHHlHhMsqfUhDhIjwZdvgYwKQNbbgZcpyrACBEG8LtXIzgTEURAi5FA3MIoPk/9lzGaM790y9uGNeaZ9RjcYelUoNZJmpb18= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8096116F2; Fri, 20 Jun 2025 05:32:57 -0700 (PDT) Received: from [10.57.27.59] (unknown [10.57.27.59]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F05803F58B; Fri, 20 Jun 2025 05:33:13 -0700 (PDT) Message-ID: <562662d4-69ca-4d0e-ad0d-fd8cece417e0@arm.com> Date: Fri, 20 Jun 2025 13:33:11 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v5 2/4] PCI: rockchip: Set Target Link Speed before retraining To: Geraldo Nascimento , linux-rockchip@lists.infradead.org Cc: Shawn Lin , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Rick wertenbroek , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <1966f8ddc4a81426b4f1f48c22bea9b4a6e6297c.1749833987.git.geraldogabriel@gmail.com> From: Robin Murphy Content-Language: en-GB In-Reply-To: <1966f8ddc4a81426b4f1f48c22bea9b4a6e6297c.1749833987.git.geraldogabriel@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 2025-06-13 6:03 pm, Geraldo Nascimento wrote: > Current code may fail Gen2 retraining if Target Link Speed > is set to 2.5 GT/s in Link Control and Status Register 2. > Set it to 5.0 GT/s accordingly. I have max-link-speed overridden to 2 in my local DTB, and indeed this seems to make my NVMe report a 5.0 GT/s link where previously it was still downgrading to 2.5, so: Tested-by: Robin Murphy > Signed-off-by: Geraldo Nascimento > --- > drivers/pci/controller/pcie-rockchip-host.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c > index 8489d51e01ca..467e3fc377f7 100644 > --- a/drivers/pci/controller/pcie-rockchip-host.c > +++ b/drivers/pci/controller/pcie-rockchip-host.c > @@ -341,6 +341,10 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) > * Enable retrain for gen2. This should be configured only after > * gen1 finished. > */ > + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); > + status &= ~PCI_EXP_LNKCTL2_TLS; > + status |= PCI_EXP_LNKCTL2_TLS_5_0GT; > + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); > rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); > status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); > status |= PCI_EXP_LNKCTL_RL;