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Wed, 30 Oct 2024 10:33:49 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49UAXnuM005413 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Oct 2024 10:33:49 GMT Received: from [10.231.207.28] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 30 Oct 2024 03:33:43 -0700 Message-ID: <563e7080-68a9-4735-995a-72baf2e35d49@quicinc.com> Date: Wed, 30 Oct 2024 18:33:41 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/2] arm64: dts: qcom: qcs615-ride: Enable PMIC peripherals To: Dmitry Baryshkov CC: , , , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , References: <20241028-adds-spmi-pmic-peripherals-for-qcs615-v3-0-f0778572ee41@quicinc.com> <20241028-adds-spmi-pmic-peripherals-for-qcs615-v3-2-f0778572ee41@quicinc.com> <38cceae8-5203-4057-bd8b-f20fe3656474@quicinc.com> Content-Language: en-US From: Tingguo Cheng In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: MwRTFt_cmggySsdospp3lmrcLuCNDEnP X-Proofpoint-GUID: MwRTFt_cmggySsdospp3lmrcLuCNDEnP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 bulkscore=0 adultscore=0 spamscore=0 phishscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 mlxscore=0 mlxlogscore=976 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410300080 On 10/28/2024 5:41 PM, Dmitry Baryshkov wrote: > On Mon, 28 Oct 2024 at 10:40, Tingguo Cheng wrote: >> >> >> >> On 10/28/2024 4:23 PM, Dmitry Baryshkov wrote: >>> On Mon, Oct 28, 2024 at 04:03:25PM +0800, Tingguo Cheng wrote: >>>> Enable PMIC and PMIC peripherals for qcs615-ride board. >>>> >>>> Signed-off-by: Tingguo Cheng >>>> --- >>>> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 15 +++++++++++++++ >>>> 1 file changed, 15 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts >>>> index ee6cab3924a6d71f29934a8debba3a832882abdd..37358f080827bbe4484c14c5f159e813810c2119 100644 >>>> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts >>>> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts >>>> @@ -6,6 +6,7 @@ >>>> >>>> #include >>>> #include "qcs615.dtsi" >>>> +#include "pm8150.dtsi" >>>> / { >>>> model = "Qualcomm Technologies, Inc. QCS615 Ride"; >>>> compatible = "qcom,qcs615-ride", "qcom,qcs615"; >>>> @@ -210,6 +211,20 @@ &rpmhcc { >>>> clocks = <&xo_board_clk>; >>>> }; >>>> >>>> +&pon { >>>> + /delete-property/ mode-bootloader; >>>> + /delete-property/ mode-recovery; >>> >>> Why? >> Because boot modes will be supported on PSCI module from another patch, >> reboot-modes are required to remove from PMIC side. > > => commit message, please. > okay, will upload v4 with other comments fixing together. >>> >>>> +}; >>>> + >>>> +&pon_pwrkey { >>>> + status = "okay"; >>>> +}; >>>> + >>>> +&pon_resin { >>>> + linux,code = ; >>>> + status = "okay"; >>>> +}; >>>> + >>>> &uart0 { >>>> status = "okay"; >>>> }; >>>> >>>> -- >>>> 2.34.1 >>>> >>> >> >> -- >> Thank you & BRs >> Tingguo >> > > -- Thank you & BRs Tingguo