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Fri, 16 Jan 2026 01:46:00 -0800 (PST) X-Received: by 2002:a05:6a21:6d86:b0:38b:e398:b9fd with SMTP id adf61e73a8af0-38dfe604ed2mr2800259637.20.1768556760234; Fri, 16 Jan 2026 01:46:00 -0800 (PST) Received: from [10.0.0.3] ([106.222.229.125]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-81fa108b23asm1647523b3a.3.2026.01.16.01.45.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Jan 2026 01:45:59 -0800 (PST) Message-ID: <564c05b4-a41d-df0a-abb8-564b22b9a45e@oss.qualcomm.com> Date: Fri, 16 Jan 2026 15:15:54 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH v4 4/6] media: iris: Move vpu register defines to common header file Content-Language: en-US To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Dmitry Baryshkov , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vishnu Reddy , Bryan O'Donoghue References: <20251210-knp_video-v4-0-8d11d840358a@oss.qualcomm.com> <20251210-knp_video-v4-4-8d11d840358a@oss.qualcomm.com> From: Dikshita Agarwal In-Reply-To: <20251210-knp_video-v4-4-8d11d840358a@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: ABtPN_NIMdD21_wRNzGhuOEHEI1MOk7V X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE2MDA2OCBTYWx0ZWRfX33B/SD+YD7fc GvMiQyYwvfoLiSsqVUTQexvVOYH3N7D0Zy3ECGemgoHo/J3poYpKsZ8Z69lYOwF9cX0Hv+PlRX4 wYdxwCOrYjaYLCdv1E3GSiRcHdCf2f4w02SQueDqQ3RGrT0/RkWcJIJj3GnzKnaqWVmrIVoxS9r Mc/KNocrciet/UBbnqd5GJxVBSSfFYRTUCHO3PRbBoRHB3v2X50CGduP14oAqyIQ4RkxvvdQoHo 0vg8QuLHN4pM8BGiYWbTDScBAaJHe82KLuECsFiaodi5rWXhVVpLZXrt1PclyhP3JNODUzV04KK QKttQ9l47284wB5xlzOiz8ZC5YxrXaWgTYPyIvow6OIDMgGqAbyIEXyG/AYpBRWRYfA94apEVpX jkSR75SINwlBERqW+ifN9FdRGENlKyqpHn6pLlbzFIAcXoQHnLbnecHJ+ZS25gJIf3ZbHKHEhRI MDxwZyD9ZvynPQzFGCQ== X-Authority-Analysis: v=2.4 cv=OJIqHCaB c=1 sm=1 tr=0 ts=696a08d9 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=blWSk0AuXjsE0o78ys1YMg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=vXM2DW8_tl7Bo0BeeMgA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: ABtPN_NIMdD21_wRNzGhuOEHEI1MOk7V X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-16_03,2026-01-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 priorityscore=1501 malwarescore=0 spamscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601160068 On 12/10/2025 6:06 PM, Vikash Garodia wrote: > Some of vpu4 register defines are common with vpu3x. Move those into the > common register defines header. This is done to reuse the defines for > vpu4 in subsequent patch which enables the power sequence for vpu4. > > Reviewed-by: Bryan O'Donoghue > Co-developed-by: Vishnu Reddy > Signed-off-by: Vishnu Reddy > Signed-off-by: Vikash Garodia > --- > drivers/media/platform/qcom/iris/iris_vpu3x.c | 42 --------------- > drivers/media/platform/qcom/iris/iris_vpu_common.c | 43 --------------- > .../platform/qcom/iris/iris_vpu_register_defines.h | 61 ++++++++++++++++++++++ > 3 files changed, 61 insertions(+), 85 deletions(-) > > diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c > index 339776a0b4672e246848c3a6a260eb83c7da6a60..cd53bcda3b3e1d6f234486df49a51150a7ec9799 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c > @@ -11,48 +11,6 @@ > #include "iris_vpu_common.h" > #include "iris_vpu_register_defines.h" > > -#define WRAPPER_TZ_BASE_OFFS 0x000C0000 > -#define AON_BASE_OFFS 0x000E0000 > -#define AON_MVP_NOC_RESET 0x0001F000 > - > -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) > -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) > -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) > -#define REQ_POWER_DOWN_PREP BIT(0) > -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) > -#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */ > -#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */ > -#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ > -#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) > -#define CORE_CLK_RUN 0x0 > -/* VPU v3.5 */ > -#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78) > - > -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) > -#define CTL_AXI_CLK_HALT BIT(0) > -#define CTL_CLK_HALT BIT(1) > - > -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) > -#define RESET_HIGH BIT(0) > - > -#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) > -#define CORE_BRIDGE_SW_RESET BIT(0) > -#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) > - > -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) > -#define MSK_SIGNAL_FROM_TENSILICA BIT(0) > -#define MSK_CORE_POWER_ON BIT(1) > - > -#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) > -#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) > - > -#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004) > - > -#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) > - > -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) > -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) > - > #define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18) > #define SW_RESET BIT(0) > #define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20) > diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c > index fef192a2de48fa47af421632829184c5896326cd..50242fc6b4653a7d74ff64500f40eb8a859a6548 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c > @@ -11,13 +11,6 @@ > #include "iris_vpu_common.h" > #include "iris_vpu_register_defines.h" > > -#define WRAPPER_TZ_BASE_OFFS 0x000C0000 > -#define AON_BASE_OFFS 0x000E0000 > - > -#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS) > - > -#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C) > -#define CLEAR_XTENSA2HOST_INTR BIT(0) > > #define CTRL_INIT (CPU_CS_BASE_OFFS + 0x48) > #define CTRL_STATUS (CPU_CS_BASE_OFFS + 0x4C) > @@ -35,42 +28,6 @@ > #define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64) > #define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68) > > -#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148) > -#define HOST2XTENSA_INTR_ENABLE BIT(0) > - > -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) > -#define MSK_SIGNAL_FROM_TENSILICA BIT(0) > -#define MSK_CORE_POWER_ON BIT(1) > - > -#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150) > -#define CPU_IC_SOFTINT_H2A_SHFT 0x0 > - > -#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C) > -#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3) > -#define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2) > - > -#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10) > -#define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3) > -#define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2) > - > -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) > -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) > -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) > -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) > - > -#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10) > -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) > -#define CTL_AXI_CLK_HALT BIT(0) > -#define CTL_CLK_HALT BIT(1) > - > -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) > -#define RESET_HIGH BIT(0) > - > -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) > -#define REQ_POWER_DOWN_PREP BIT(0) > - > -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) > - > static void iris_vpu_interrupt_init(struct iris_core *core) > { > u32 mask_val; > diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h > index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..72168b9ffa7385d53d7190265d1c0922ee04a656 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h > +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h > @@ -7,11 +7,72 @@ > #define __IRIS_VPU_REGISTER_DEFINES_H__ > > #define VCODEC_BASE_OFFS 0x00000000 > +#define AON_MVP_NOC_RESET 0x0001F000 > #define CPU_BASE_OFFS 0x000A0000 > #define WRAPPER_BASE_OFFS 0x000B0000 > +#define WRAPPER_TZ_BASE_OFFS 0x000C0000 > +#define AON_BASE_OFFS 0x000E0000 > + > +#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) > + > +#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) > +#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) > + > +#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004) > > #define CPU_CS_BASE_OFFS (CPU_BASE_OFFS) > +#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS) > + > +#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C) > +#define CLEAR_XTENSA2HOST_INTR BIT(0) > + > +#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148) > +#define HOST2XTENSA_INTR_ENABLE BIT(0) > + > +#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150) > +#define CPU_IC_SOFTINT_H2A_SHFT 0x0 > + > +#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) > +#define CORE_BRIDGE_SW_RESET BIT(0) > +#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) > + > +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) > +#define MSK_SIGNAL_FROM_TENSILICA BIT(0) > +#define MSK_CORE_POWER_ON BIT(1) > > +#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C) > +#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3) > +#define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2) > + > +#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10) > +#define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3) > +#define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2) > + > +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) > +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) > +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) > +#define REQ_POWER_DOWN_PREP BIT(0) > + > +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) > +#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */ > +#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */ > +#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ > + > +#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78) > #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80) > +#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) > +#define CORE_CLK_RUN 0x0 > + > +#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10) > + > +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) > +#define CTL_AXI_CLK_HALT BIT(0) > +#define CTL_CLK_HALT BIT(1) > + > +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) > +#define RESET_HIGH BIT(0) > + > +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) > +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) > > #endif > Reviewed-by: Dikshita Agarwal Thanks, Dikshita