From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756237AbbJIIS4 (ORCPT ); Fri, 9 Oct 2015 04:18:56 -0400 Received: from mout.kundenserver.de ([212.227.17.13]:65452 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933355AbbJIISq (ORCPT ); Fri, 9 Oct 2015 04:18:46 -0400 From: Arnd Bergmann To: Marc Zyngier Cc: Bharat Kumar Gogada , "robh+dt@kernel.org" , "pawel.moll@arm.com" , "mark.rutland@arm.com" , "ijc+devicetree@hellion.org.uk" , "galak@codeaurora.org" , Michal Simek , Soren Brinkmann , "bhelgaas@google.com" , "tinamdar@apm.com" , "treding@nvidia.com" , "rjui@broadcom.com" , "Minghuan.Lian@freescale.com" , "m-karicheri2@ti.com" , "hauke@hauke-m.de" , "devicetree@vger.kernel.org" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Ravikiran Gummaluri , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v3] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller Date: Fri, 09 Oct 2015 10:18:21 +0200 Message-ID: <5676910.8cxuyuvhpA@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: <56177669.2000302@arm.com> References: <1444146289-28940-1-git-send-email-bharatku@xilinx.com> <8520D5D51A55D047800579B09414719801690CD0@XAP-PVEXMBX01.xlnx.xilinx.com> <56177669.2000302@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:tWt0HjKUGj8Pp9+UQvy0625m2yLnaj61qcUQJHVrJHO+SSXWog7 GJ4/VbJxmD2CXAKHuIZkqxh/P2/jieZneIiG9+ePNsaeMgOu7KBBzaudqnsjQIIHhfXARxO C0Hxz/1+Uc3lg3jmWrJb3OgrgTlTivslMSGrfu4rSqFEobRgGqD9AETy/KX69sMNj4/p6B5 j2EUZfpHAmjyezvrgxgPw== X-UI-Out-Filterresults: notjunk:1;V01:K0:Xt8OxzuIe9c=:cKT8FmUj09a/baVFcWZTtd XWb+P9n1refsThCa9QtaKCvM8KkHadGK1A7/tmr9T0S/VZ6+8Y6EItltBc5O1/Tfz34e/357F x7R0Uh/U7LeOCZDX8S0z3s5Ejsp/XtVYWLkwGvpIEG+2ta642zUikLxlSRQkiNY6wJQIC4+0z hVub+imaZQcF4S4zJBhn0T9Lsi9mxpa75zICLUfLZC9KlD8xPEmDFpdYnog+3M9kzz94J9FtB IfjfseZXuC0C1nwj2a2VfdMiU6Siqll0GNXMADHYuXzr2OGjMjJ3KVDOD+RSUxUDw11WdmaaX 7kcpIFDVUfME3nZHfZ8m928HUXmguV/EfinY0vDSgntHMMUl9qK9Zq7nvh4G6bkyvk//qoq2A 7G70TEJyKgoRUx+JYQ/EE2kMVb0P5iufiKA8GlB2u/G4DnQsSKZJUDl3wxH1rFMfM6HU4WHqg tSfcnnYAW8uRMmKRCjYrqIUgYe5LyMZN2VmL8zau9AOkk3R2DSb9iufkrVOoAD/peelknAdjt VwhWO/QrUbb1YztbKvUekDK4I2vmkvgT9sFfEgrWVp+qMDmA67A5EzrDfQR683R8mlMy0flwL tzKuEK3DVxgrrnIitwlrRzIasaZi+x6iwnDnCTdgUKAIaFuLChA5RekMpilBrvhka52aKxAZ7 +JlRuJJiDTSHGGk2RDL400sbntDucmuA9FZXOmRzntN+ZAIBYP+RBxcBnloqlSMQNCdMadm+q myFpX6iW0qDVnySg Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Friday 09 October 2015 09:10:17 Marc Zyngier wrote: > > Please let me know whether we require a separate msi file as > > suggested in your previous comments to separate MSI controller and > > PCIE controller in two files, if we don't have separate node. If we > > do not need a separate node do we need to embed MSI controller child > > node in PCIe controller node itself, and what properties does this > > child node will require other than 'interrupts'. > > If you want to keep them in the same file, please at least have two > separate patches. These are two different functions, and they should be > reviewed separately. > > It will help everyone to understand your code, and speed up the > reviewing process. Agreed. Also, the part we really want is to have the PCI controller code decoupled enough from the MSI code that it will not require further changes once Xilinx comes out with a chip that has a modern GIC in it and the same PCIe host. Arnd