From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752882AbcADFwf (ORCPT ); Mon, 4 Jan 2016 00:52:35 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:54502 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751271AbcADFwc convert rfc822-to-8bit (ORCPT ); Mon, 4 Jan 2016 00:52:32 -0500 X-AuditID: cbfee68d-f79646d000001355-13-568a089e1022 MIME-version: 1.0 Content-type: text/plain; charset=utf-8 Content-transfer-encoding: 8BIT Message-id: <568A089B.20109@samsung.com> Date: Mon, 04 Jan 2016 14:52:27 +0900 From: Jaehoon Chung User-Agent: Mozilla/5.0 (X11; Linux i686; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 To: Shawn Lin , Ulf Hansson Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] mmc: dw_mmc: add hw_reset support References: <1451875854-12521-1-git-send-email-shawn.lin@rock-chips.com> In-reply-to: <1451875854-12521-1-git-send-email-shawn.lin@rock-chips.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprDIsWRmVeSWpSXmKPExsWyRsSkQHceR1eYQdc8Q4vLu+awWRz5389o cefJelaL42vDHVg87lzbw+bxd9Z+Fo/Pm+QCmKO4bFJSczLLUov07RK4MmasYCnoV6/Y+961 gXGGfBcjJ4eEgInEx7u7mCFsMYkL99azdTFycQgJrGCUaG19xwZTtLrrNFRiKaPE8YWbwDp4 BQQlfky+x9LFyMHBLKAuMWVKLkiYWUBEoqXhOSuErS2xbOFrZojeB4wSl6bPZgep5xXQkFh8 oBbEZBFQlVj7Ox6knE1AR2L7t+NMILaoQJjEg3V7wcaICPhJbN2xlQ1ipLXEzx+tYHFhAUuJ pY3/GEFsIQEPiRkt79lBbE4BT4lZc9eBrZUQWMcu8eb2YbBmFgEBiW+TD4GdLCEgK7HpANTv khIHV9xgmcAoPgvJY7MQHpuF5LFZSB5bwMiyilE0tSC5oDgpvchQrzgxt7g0L10vOT93EyMw 0k7/e9a7g/H2AetDjAIcjEo8vB8+dYYJsSaWFVfmHmI0BTpoIrOUaHI+MJ7zSuINjc2MLExN TI2NzC3NlMR5FaV+BgsJpCeWpGanphakFsUXleakFh9iZOLglGpg1MywNKp7fkn318nQ+TlK 05tv71Of0uyRE+3DeS/bzjnkBZMNAzvv5tWH/4dzWKg/0NPeIcXQeV6s4asf242F2ce+570y YpSca9b9avI8ya3bW/7OO9gjuOGMdfXSLfFpi+ZJPGRWnpTX+2D6HLP+e4kW3Z5TTxVmxh+a fi/AltnfOY7pmoSCEktxRqKhFnNRcSIAJjio4q8CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrAIsWRmVeSWpSXmKPExsVy+t9jAd15HF1hBrsPaVtc3jWHzeLI/35G iztP1rNaHF8b7sDicefaHjaPv7P2s3h83iQXwBzVwGiTkZqYklqkkJqXnJ+SmZduq+QdHO8c b2pmYKhraGlhrqSQl5ibaqvk4hOg65aZA7RNSaEsMacUKBSQWFyspG+HaUJoiJuuBUxjhK5v SBBcj5EBGkhYw5jx/vlk9oKTahWrl8U3MF6S62Lk5JAQMJFY3XWaDcIWk7hwbz2QzcUhJLCU UeL4wk3MIAleAUGJH5PvsXQxcnAwC8hLHLmUDWGqS0yZkgtR/oBR4tL02ewgcV4BDYnFB2pB TBYBVYm1v+NBhrAJ6Ehs/3acCcQWFQiTeLBuLyuILSLgJ7F1x1awC5gFrCV+/mgFiwsLWEos bfzHCGILCXhIzGh5zw5icwp4Ssyau455AqPALCS3zUK4bRbCbQsYmVcxSqQWJBcUJ6XnGuWl lusVJ+YWl+al6yXn525iBMfmM+kdjId3uR9iFOBgVOLh9fjaGSbEmlhWXJl7iFGCg1lJhPf9 CaAQb0piZVVqUX58UWlOavEhRlOg7yYyS4km5wPTRl5JvKGxiZmRpZG5oYWRsbmSOO++S5Fh QgLpiSWp2ampBalFMH1MHJxSDYzbIiYGGgXw6tnkH9yurnYkKU6xyrOwLfJlg+KyjPuv/60+ dOyM47fNF0rMbv8pNSwMrn/75thT26XtIXYRf0RKln6Ole7Y3bhx5l+nkkNM64/tCjIrbrql umtek48rp9R9Od9ZXZW7t2vyhhz4v/Jvf/D9CytamMtVDmRp7f9g8enmJtWGDRFKLMUZiYZa zEXFiQA1FcMg4wIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Shawn. On 01/04/2016 11:50 AM, Shawn Lin wrote: > This patch implement hw_reset function for DesignWare > MMC controller. By adding this feature, mmc blk can > do some basic recovery. > >>>From Synopsys DesignWare Cores Mobile Storage Host Databook > (Section 7.4.4), we get the details: > 1. Program CMD12 to end any transfer in process. > 2. Wait for DTO, even if no response is sent back by the card. > 3. Set the following resets: > Software reset – BMOD[0] for IDMAC only > DMA reset– CTRL[2] > FIFO reset – CTRL[1] bits > 4. Program the CARD_RESET register with a value of 0 for the bit > corresponding to the card number; This can be done at any time when > the card is connected to the controller. This programming asserts the > RST_n signal and resets the card. > 5. Wait for minimum of 1 μs or cclk_in period, which ever is greater > 6. After a minimum of 1 μs, the application should program a value of > 0 into the CARD_RESET register for the bit corresponding to the card > number. This de-asserts the RST_n signal and takes the card out of reset. > 7. The application can program a new CMD only after a minimum of 200 us > after the de-assertion of the RST_n signal, as per the MMC 4.41 standard. > > HW reset producer will be call in mmc_init_card before mmc_go_idle. At that > time，dw mmc hasn't update clk for itself, so CMD12 is inappropriate and > unnecessary. Moreover, if mmc device runs into broken states, DRTO or RTO > generated by previous cmd w/ data will make mmc core issue stop already. Then > it will retry again and again, issue stop and card status again until the > cmd's retry number decrease to zero. That will finally trigger HW reset producer > if we declare MMC_CAP_HW_RESET. So there's no need to do step 1 and 2 for the > reasons we mentioned above. Which IP version did you use? Could you share it..? Did you know about CHIP RESET sequence? > > This implementation can be easily tested by cutting off->On vmmc while doing data > accessing in background to simulate that case. And dw_mmc can generate timeout > interrupt and make mmc core trigger hw reset producer before re-init mmc card > to recover itself. > > Signed-off-by: Shawn Lin > > --- > > Changes in v2: > - remove unecessary mb > - reduce time cost for hw_reset > - combine SDMMC_CTRL_DMA_RESET and SDMMC_CTRL_FIFO_RESET > > drivers/mmc/host/dw_mmc.c | 25 +++++++++++++++++++++++++ > drivers/mmc/host/dw_mmc.h | 4 ++++ > 2 files changed, 29 insertions(+) > > diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c > index 7128351..98e75fc 100644 > --- a/drivers/mmc/host/dw_mmc.c > +++ b/drivers/mmc/host/dw_mmc.c > @@ -1477,6 +1477,30 @@ static int dw_mci_get_cd(struct mmc_host *mmc) > return present; > } > > +static void dw_mci_hw_reset(struct mmc_host *mmc) > +{ > + struct dw_mci_slot *slot = mmc_priv(mmc); > + struct dw_mci *host = slot->host; > + > + if (host->use_dma == TRANS_MODE_IDMAC) > + dw_mci_idmac_reset(host); > + > + if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | > + SDMMC_CTRL_FIFO_RESET)) > + return; > + > + /* > + * According to eMMC spec, card reset procedure: > + * tRstW >= 1us: RST_n pulse width > + * tRSCA >= 200us: RST_n to Command time > + * tRSTH >= 1us: RST_n high period > + */ > + mci_writel(slot->host, RST_N, SDMMC_RST_HWRESET); Even though we used only one slot, but it needs to control bit with slot->id. Best Regards, Jaehoon Chung > + usleep_range(1, 2); > + mci_writel(slot->host, RST_N, SDMMC_RST_HWACTIVE); > + usleep_range(200, 300); > +} > + > static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) > { > struct dw_mci_slot *slot = mmc_priv(mmc); > @@ -1563,6 +1587,7 @@ static const struct mmc_host_ops dw_mci_ops = { > .set_ios = dw_mci_set_ios, > .get_ro = dw_mci_get_ro, > .get_cd = dw_mci_get_cd, > + .hw_reset = dw_mci_hw_reset, > .enable_sdio_irq = dw_mci_enable_sdio_irq, > .execute_tuning = dw_mci_execute_tuning, > .card_busy = dw_mci_card_busy, > diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h > index f695b58..684ee34 100644 > --- a/drivers/mmc/host/dw_mmc.h > +++ b/drivers/mmc/host/dw_mmc.h > @@ -46,6 +46,7 @@ > #define SDMMC_VERID 0x06c > #define SDMMC_HCON 0x070 > #define SDMMC_UHS_REG 0x074 > +#define SDMMC_RST_N 0x078 > #define SDMMC_BMOD 0x080 > #define SDMMC_PLDMND 0x084 > #define SDMMC_DBADDR 0x088 > @@ -169,6 +170,9 @@ > #define SDMMC_IDMAC_ENABLE BIT(7) > #define SDMMC_IDMAC_FB BIT(1) > #define SDMMC_IDMAC_SWRESET BIT(0) > +/* H/W reset */ > +#define SDMMC_RST_HWACTIVE 0x1 > +#define SDMMC_RST_HWRESET 0x0 > /* Version ID register define */ > #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) > /* Card read threshold */ >