Re: [PATCH V1 04/10] thermal: tegra: add T210-specific SOC_THERM driver

[Wei Ni <wni@nvidia.com>]

On 2016年01月13日 23:06, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Wed, Jan 13, 2016 at 03:58:43PM +0800, Wei Ni wrote:
> [...]
>> diff --git a/drivers/thermal/tegra/tegra_soctherm_fuse.c b/drivers/thermal/tegra/tegra_soctherm_fuse.c
>> index 7c608698f1ae..22f402240672 100644
>> --- a/drivers/thermal/tegra/tegra_soctherm_fuse.c
>> +++ b/drivers/thermal/tegra/tegra_soctherm_fuse.c
>> @@ -28,6 +28,17 @@
>>  #define FUSE_TSENSOR_COMMON			0x180
>>  
>>  /*
>> + * T210: Layout of bits in FUSE_TSENSOR_COMMON:
>> + *    3                   2                   1                   0
>> + *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
>> + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
>> + * |       BASE_FT       |      BASE_CP      | SHFT_FT | SHIFT_CP  |
>> + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
>> + *
>> + * In chips prior to T210, this fuse was incorrectly sized as 26 bits,
>> + * and didn't hold SHIFT_CP in [31:26]. Therefore these missing six bits
> 
> The above diagram aso doesn't contain SHIFT_CP in bits [31:26] but
> rather in bits [5:0]. Which one is correct: the text or the diagram?

Hmm, sorry for the confusion. The diagram is for Tegra210, and the text is used
to explain why the Tegra124 would use the FUSE_SPARE_REALIGNMENT_REG.
For Tegra210, the FUSE_TSENSOR_COMMON contain four values, including SHIFT_CP in
the bits of [5:0]
But for Tegra124, the FUSE_TSENSOR_COMMON only contain three values, the
SHIFT_CP is in the FUSE_SPARE_REALIGNMENT_REG which didn't be used in Tegra210.
I will move the text under the line of "* T12x, etc: FUSE_TSENSOR_COMMON:", so
that it will be more readable.

> 
> Thierry
> 
> * Unknown Key
> * 0x7F3EB3A1
>