I also put the earlier reduction tests and the newer controls here:
https://forge.caseytunturi.com/Fimeg/hp-envy-27-p014-hda
Much of the reduction was already done before I sent v1. Runs A through G progressively removed the RINTCNT change, PCI command cycle, IRQ quiescing, abnormal controller init, and clock-gate handling... just standard chew of too much code. The remaining behavior that consistently brought cad0 back was the tight CRST sequence.
> Can't the standard snd_hdac_bus_reset_link() work? If not, we mayI tested snd_hdac_bus_reset_link(bus, true) at the same probe point. In that test it left STATESTS at 0x4 and only HDMI enumerated. Restoring the reduced tight-reset version brought cad0 back.
I also tested with the probe reset removed entirely. That gives HDMI only, including from a cold boot. The source variants, module hashes, and logs for those tests are in the archive above - and I'm happy to double check.
With the board on the power-save denylist, removing the system-resume reset leaves cad0 registered after S3, but codec commands time out and capture fails. With the reset restored, capture works after the same deep S3 test.
I do not have a narrower condition for the reset yet.
I haven't tested S4.
> Trying the bus reset at probe is understandable, but...
> ... those look too ugly. The use of PIO mode isn't mentioned in the description, either. Maybe PIO mode should be used always for your board?