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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76bccfbd98csm29222812b3a.67.2025.08.12.05.57.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Aug 2025 05:57:12 -0700 (PDT) Message-ID: <56c18c70-ebb9-4018-b8b6-9041337bb3c3@rivosinc.com> Date: Tue, 12 Aug 2025 14:57:02 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [External] [PATCH v6 3/5] drivers: firmware: add riscv SSE support To: yunhui cui Cc: Paul Walmsley , Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Himanshu Chauhan , Anup Patel , Xu Lu , Atish Patra , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Conor Dooley References: <20250808153901.2477005-1-cleger@rivosinc.com> <20250808153901.2477005-4-cleger@rivosinc.com> Content-Language: en-US From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 12/08/2025 14:54, yunhui cui wrote: >> &preferred_hart); >> + if (ret) >> + goto err_event_free; >> + >> + cpu = riscv_hartid_to_cpuid(preferred_hart); >> + sse_global_event_update_cpu(event, cpu); >> + >> + ret = sse_sbi_register_event(event, event->global); >> + if (ret) >> + goto err_event_free; >> + >> + } else { >> + sse_on_each_cpu(event, SBI_SSE_EVENT_REGISTER, >> + SBI_SSE_EVENT_DISABLE); >> + } > It is necessary to check the return value; otherwise, the event might > be passed as a valid value to subsequent logic, such as > sse_event_enable(). > > Hi Yunhui, Indeed, nice catch. I'll fix that. Thanks, Clément