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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org,
	Catalin Marinas <catalin.marinas@arm.com>,
	Marc Zyngier <maz@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH V3 02/16] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register
Date: Tue, 5 May 2020 12:20:41 +0530	[thread overview]
Message-ID: <56cd3062-a0c2-6cdf-b7c6-c2b7bf56d23b@arm.com> (raw)
In-Reply-To: <20200504202453.GA5012@willie-the-truck>



On 05/05/2020 01:54 AM, Will Deacon wrote:
> On Sat, May 02, 2020 at 07:03:51PM +0530, Anshuman Khandual wrote:
>> ID_DFR0 based TraceFilt feature should not be exposed to guests. Hence lets
>> drop it.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Marc Zyngier <maz@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: James Morse <james.morse@arm.com>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>>
>> Suggested-by: Mark Rutland <mark.rutland@arm.com>
>> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>  arch/arm64/kernel/cpufeature.c | 1 -
>>  1 file changed, 1 deletion(-)
>>
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index 6d032fbe416f..51386dade423 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -435,7 +435,6 @@ static const struct arm64_ftr_bits ftr_id_pfr1[] = {
>>  };
>>  
>>  static const struct arm64_ftr_bits ftr_id_dfr0[] = {
>> -	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
> 
> Hmm, this still confuses me. Is this not now FTR_NONSTRICT? Why is that ok?

Mark had mentioned about it earlier (https://patchwork.kernel.org/patch/11287805/)
Did I misinterpret the first part ? Could not figure "capping the emulated debug
features" part. Probably, Mark could give some more details.

From the earlier discussion:

* ID_DFR0 fields need more thought; we should limit what we expose here.
  I don't think it's valid for us to expose TraceFilt, and I suspect we
  need to add capping for debug features we currently emulate.

  reply	other threads:[~2020-05-05  6:51 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-02 13:33 [PATCH V3 00/16] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 01/16] arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 02/16] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register Anshuman Khandual
2020-05-04 20:24   ` Will Deacon
2020-05-05  6:50     ` Anshuman Khandual [this message]
2020-05-05 10:42       ` Will Deacon
2020-05-08  4:25         ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 03/16] arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0 Anshuman Khandual
2020-05-05 11:10   ` Will Deacon
2020-05-08  4:59     ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 04/16] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual
2020-05-05 11:12   ` Will Deacon
2020-05-05 11:16     ` Mark Rutland
2020-05-05 11:18       ` Mark Rutland
2020-05-05 11:27       ` Will Deacon
2020-05-05 11:50         ` Mark Rutland
2020-05-05 12:12           ` Will Deacon
2020-05-05 12:49             ` Mark Rutland
2020-05-08  8:32     ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 05/16] arm64/cpufeature: Introduce ID_DFR1 " Anshuman Khandual
2020-05-03 21:35   ` Suzuki K Poulose
2020-05-02 13:33 ` [PATCH V3 06/16] arm64/cpufeature: Introduce ID_MMFR5 " Anshuman Khandual
2020-05-04 20:33   ` Will Deacon
2020-05-05  7:01     ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 07/16] arm64/cpufeature: Add remaining feature bits in ID_PFR0 register Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 08/16] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register Anshuman Khandual
2020-05-05 11:14   ` Will Deacon
2020-05-06  6:43     ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 09/16] arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register Anshuman Khandual
2020-05-05  4:54   ` Suzuki K Poulose
2020-05-05  7:06     ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 10/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register Anshuman Khandual
2020-05-05  4:59   ` Suzuki K Poulose
2020-05-06  6:35     ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 11/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register Anshuman Khandual
2020-05-05  9:24   ` Suzuki K Poulose
2020-05-06  6:33     ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 12/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 13/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 14/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 15/16] arm64/cpufeature: Add remaining feature bits in ID_AA64DFR0 register Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 16/16] arm64/cpufeature: Replace all open bits shift encodings with macros Anshuman Khandual

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