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X-CSE-ConnectionGUID: PszW2Y5dQZK+ib58tu9fHQ== X-CSE-MsgGUID: U7Zx1BsYRP+0a3enMhUULA== X-IronPort-AV: E=McAfee;i="6700,10204,11267"; a="44029367" X-IronPort-AV: E=Sophos;i="6.12,182,1728975600"; d="scan'208";a="44029367" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Nov 2024 05:40:21 -0800 X-CSE-ConnectionGUID: Vqf6dgSQR/y3Xnpn7Cnk1w== X-CSE-MsgGUID: xukq6NshT/eYbq2TSz+lHw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,182,1728975600"; d="scan'208";a="92058743" Received: from ahunter6-mobl1.ger.corp.intel.com (HELO [10.0.2.15]) ([10.245.115.59]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Nov 2024 05:40:16 -0800 Message-ID: <56db8257-6da2-400d-8306-6e21d9af81f8@intel.com> Date: Mon, 25 Nov 2024 15:40:10 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC 1/7] x86/virt/tdx: Add SEAMCALL wrapper to enter/exit TDX guest To: Dave Hansen , pbonzini@redhat.com, seanjc@google.com, kvm@vger.kernel.org, dave.hansen@linux.intel.com Cc: rick.p.edgecombe@intel.com, kai.huang@intel.com, reinette.chatre@intel.com, xiaoyao.li@intel.com, tony.lindgren@linux.intel.com, binbin.wu@linux.intel.com, dmatlack@google.com, isaku.yamahata@intel.com, nik.borisov@suse.com, linux-kernel@vger.kernel.org, x86@kernel.org, yan.y.zhao@intel.com, chao.gao@intel.com, weijiang.yang@intel.com References: <20241121201448.36170-1-adrian.hunter@intel.com> <20241121201448.36170-2-adrian.hunter@intel.com> <0226840c-a975-42a5-9ddf-a54da7ef8746@intel.com> Content-Language: en-US From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki In-Reply-To: <0226840c-a975-42a5-9ddf-a54da7ef8746@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 22/11/24 18:33, Dave Hansen wrote: > On 11/22/24 03:10, Adrian Hunter wrote: >> +struct tdh_vp_enter_tdcall { >> + u64 reg_mask : 32, >> + vm_idx : 2, >> + reserved_0 : 30; >> + u64 data[TDX_ERR_DATA_PART_2]; >> + u64 fn; /* Non-zero for hypercalls, zero otherwise */ >> + u64 subfn; >> + union { >> + struct tdh_vp_enter_vmcall vmcall; >> + struct tdh_vp_enter_gettdvmcallinfo gettdvmcallinfo; >> + struct tdh_vp_enter_mapgpa mapgpa; >> + struct tdh_vp_enter_getquote getquote; >> + struct tdh_vp_enter_reportfatalerror reportfatalerror; >> + struct tdh_vp_enter_cpuid cpuid; >> + struct tdh_vp_enter_mmio mmio; >> + struct tdh_vp_enter_hlt hlt; >> + struct tdh_vp_enter_io io; >> + struct tdh_vp_enter_rd rd; >> + struct tdh_vp_enter_wr wr; >> + }; >> +}; > > Let's say someone declares this: > > struct tdh_vp_enter_mmio { > u64 size; > u64 mmio_addr; > u64 direction; > u64 value; > }; > > How long is that going to take you to debug? When adding a new hardware definition, it would be sensible to check the hardware definition first before checking anything else. However, to stop existing members being accidentally moved, could add: #define CHECK_OFFSETS_EQ(reg, member) \ BUILD_BUG_ON(offsetof(struct tdx_module_args, reg) != offsetof(union tdh_vp_enter_args, member)); CHECK_OFFSETS_EQ(r12, tdcall.mmio.size); CHECK_OFFSETS_EQ(r13, tdcall.mmio.direction); CHECK_OFFSETS_EQ(r14, tdcall.mmio.mmio_addr); CHECK_OFFSETS_EQ(r15, tdcall.mmio.value);