Re: [PATCH v3 27/46] perf print-events: Print legacy cache events for each PMU

[Ravi Bangoria <ravi.bangoria@amd.com>]

On 29-Apr-23 11:04 AM, Ian Rogers wrote:
> Mirroring parse_events_add_cache, list the legacy name alongside its
> alias with the PMU. Remove the now unnecessary hybrid logic.

Before patch:

```
$ sudo ./perf list
  ...
  duration_time                                      [Tool event]
  user_time                                          [Tool event]
  system_time                                        [Tool event]
  L1-dcache-loads                                    [Hardware cache event]
  L1-dcache-load-misses                              [Hardware cache event]
  L1-dcache-prefetches                               [Hardware cache event]
  L1-icache-loads                                    [Hardware cache event]
  L1-icache-load-misses                              [Hardware cache event]
  dTLB-loads                                         [Hardware cache event]
  dTLB-load-misses                                   [Hardware cache event]
  iTLB-loads                                         [Hardware cache event]
  iTLB-load-misses                                   [Hardware cache event]
  branch-loads                                       [Hardware cache event]
  branch-load-misses                                 [Hardware cache event]
  branch-brs OR cpu/branch-brs/                      [Kernel PMU event]
  branch-instructions OR cpu/branch-instructions/    [Kernel PMU event]
  branch-misses OR cpu/branch-misses/                [Kernel PMU event]
  ...
```

After patch:

```
$ sudo ./perf list
  ...
  duration_time                                      [Tool event]
  user_time                                          [Tool event]
  system_time                                        [Tool event]

cpu:
  L1-dcache-loads OR cpu/L1-dcache-loads/
  L1-dcache-load-misses OR cpu/L1-dcache-load-misses/
  L1-dcache-prefetches OR cpu/L1-dcache-prefetches/
  L1-icache-loads OR cpu/L1-icache-loads/
  L1-icache-load-misses OR cpu/L1-icache-load-misses/
  dTLB-loads OR cpu/dTLB-loads/
  dTLB-load-misses OR cpu/dTLB-load-misses/
  iTLB-loads OR cpu/iTLB-loads/
  iTLB-load-misses OR cpu/iTLB-load-misses/
  branch-loads OR cpu/branch-loads/
  branch-load-misses OR cpu/branch-load-misses/
  branch-brs OR cpu/branch-brs/                      [Kernel PMU event]
  branch-instructions OR cpu/branch-instructions/    [Kernel PMU event]
  branch-misses OR cpu/branch-misses/                [Kernel PMU event]
  ...
```

Is this intentional change?


> -	for (int type = 0; type < PERF_COUNT_HW_CACHE_MAX; type++) {
> -		for (int op = 0; op < PERF_COUNT_HW_CACHE_OP_MAX; op++) {
> -			/* skip invalid cache type */
> -			if (!evsel__is_cache_op_valid(type, op))
> -				continue;
> +	while ((pmu = perf_pmu__scan(pmu)) != NULL) {
> +		/*
> +		 * Skip uncore PMUs for performance. Software PMUs can open
> +		 * PERF_TYPE_HW_CACHE, so skip.

This statement is bit confusing. Can you please explain how SW pmus can
open cache events.