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Tue, 30 Jun 2026 21:07:11 -0700 (PDT) X-Received: by 2002:a05:7300:6d95:b0:305:56a:c38f with SMTP id 5a478bee46e88-30eff2a2572mr11010eec.26.1782878830841; Tue, 30 Jun 2026 21:07:10 -0700 (PDT) Received: from [10.218.5.182] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30ef03a6f9asm7249363eec.19.2026.06.30.21.07.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 Jun 2026 21:07:10 -0700 (PDT) Message-ID: <56ebd97b-0834-41ac-8fdb-2469e2848694@oss.qualcomm.com> Date: Wed, 1 Jul 2026 09:37:04 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: qcom: enable ALWAYS_ON for titan_top_gdsc To: Konrad Dybcio , Brian Masney , Bjorn Andersson , Michael Turquette , Stephen Boyd , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das References: <20260626-camcc-sc8280xp-titan-top-v1-1-2ca246886493@redhat.com> Content-Language: en-US From: Jagadeesh Kona In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Co2PtH4D c=1 sm=1 tr=0 ts=6a449270 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=uyBkinp2FPxe1pn4hbAA:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-ORIG-GUID: UUzZbgQXuqMJVIP2MAk79MxFoCgORwt- X-Proofpoint-Spam-Info: AW1haW4tMjYwNzAxMDAzOCBTYWx0ZWRfX3nipoiFhfBws FsqRio9+n3LOCQ0UA03msuQ0aNXV1VUN/YR34m2N30Ed4D+2uqFFJtxF1ElcHoVuPGYj22ACtpW CZz0jlgXCKxlsHeqsFAeRtIPSTGTsOo= X-Proofpoint-GUID: UUzZbgQXuqMJVIP2MAk79MxFoCgORwt- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzAxMDAzOCBTYWx0ZWRfXwy5rja7rXegx fNtx4fyBIOhbeUVfUqZAtBjlsqvZlTq9OqGB/ANjI7ymLZMS+0SqggapyoD+5Lu/R2aYTd5Clib BZL2UMp/Paj2dGaHztZVybq/aoHXqobWNlcasHfMErgl7CTshwVAQDCk3EjuDWtme3SuXHqg3tE CQAHNb6NeMNLj59Mq6joAs5LFHs3YqaCS2Fi4y5ytIJTBuDjG023nQLcU4bSGYAlo0mJdUMVkCK hb/VS6YNqcyvEgQr6/g08nnmOtxnSj4qKFjlEPiJneS4AsrmxsrmntTdgFfm0mJ2nAQmX712YN3 UgGX2ln7FlnoF7po20XK5GJLWiy4ruZemO0Dob3cNDqPTHqUMlcEaqttPbQSSL2NcYWUBBvzEHs RwJnCtb0MDnyeUn5mu873zEjuoEFBU6JukYoySi5DgFw4BkXbraJvBrQR29p63GH2zR2RhgSpm6 R3/+UzLahUbsZ8RyrGw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-07-01_01,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 bulkscore=0 suspectscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607010038 On 6/26/2026 10:02 PM, Konrad Dybcio wrote: > On 6/26/26 6:26 PM, Brian Masney wrote: >> With the introduction of sync_state support in the clk and pmdomain >> subsystems, the following warning happens when the unused clocks are >> shutdown in camcc-sc8280xp: > > Stuck at _on_ sounds wrong.. does clk_ignore_unused / removing > the sync state from the clock part only resolve this? There may > be a clock dependency for the TITAN_TOP_GDSC that we're failing to > describe > Hi Brian, This probably could be due to camcc_gdsc_clk getting turned OFF during the sync_state, but this clk is required for GDSC transitions. The camcc_gdsc_clk is currently kept always ON from probe in camcc-sc8280xp, but the clock is also modeled with clock framework, so the clock can get disabled in sync_state callback now. Can you please try removing the modelling of camcc_gdsc_clk using below diff and see if helps here? diff --git a/drivers/clk/qcom/camcc-sc8280xp.c b/drivers/clk/qcom/camcc-sc8280xp.c index e97b8d4f3c84..660d8655d391 100644 --- a/drivers/clk/qcom/camcc-sc8280xp.c +++ b/drivers/clk/qcom/camcc-sc8280xp.c @@ -1753,24 +1753,6 @@ static struct clk_branch camcc_csiphy3_clk = { }, }; -static struct clk_branch camcc_gdsc_clk = { - .halt_reg = 0xc1e4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xc1e4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "camcc_gdsc_clk", - .parent_hws = (const struct clk_hw*[]){ - &camcc_xo_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch camcc_icp_ahb_clk = { .halt_reg = 0xc0d8, .halt_check = BRANCH_HALT, @@ -2839,7 +2821,6 @@ static struct clk_regmap *camcc_sc8280xp_clocks[] = { [CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr, [CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr, [CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr, - [CAMCC_GDSC_CLK] = &camcc_gdsc_clk.clkr, [CAMCC_ICP_AHB_CLK] = &camcc_icp_ahb_clk.clkr, [CAMCC_ICP_CLK] = &camcc_icp_clk.clkr, [CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr, Thanks, Jagadeesh