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[66.131.184.68]) by smtp.gmail.com with ESMTPSA id l5sm3411632qkf.55.2021.06.04.10.27.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Jun 2021 10:27:23 -0700 (PDT) Subject: Re: [PATCH v2 2/2] dt-bindings: clock: add QCOM SM8350 display clock bindings To: Stephen Boyd , linux-arm-msm@vger.kernel.org Cc: Rob Herring , Andy Gross , Bjorn Andersson , Michael Turquette , Rob Herring , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20210519001802.1863-1-jonathan@marek.ca> <20210519001802.1863-2-jonathan@marek.ca> <162266925581.4130789.10178141366818328902@swboyd.mtv.corp.google.com> From: Jonathan Marek Message-ID: <56f3b0bd-5dd7-80d4-041a-0fd2daf4b1f2@marek.ca> Date: Fri, 4 Jun 2021 13:25:41 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <162266925581.4130789.10178141366818328902@swboyd.mtv.corp.google.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/2/21 5:27 PM, Stephen Boyd wrote: > Quoting Jonathan Marek (2021-05-18 17:18:02) >> Add sm8350 DISPCC bindings, which are simply a symlink to the sm8250 >> bindings. Update the documentation with the new compatible. >> >> Signed-off-by: Jonathan Marek >> Reviewed-by: Rob Herring >> --- >> .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 6 ++++-- >> include/dt-bindings/clock/qcom,dispcc-sm8350.h | 1 + > >> 2 files changed, 5 insertions(+), 2 deletions(-) >> create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h > > Why the symlink? Can we have the dt authors use the existing header file > instead? > It would be strange to include bindings with the name of a different SoC. I guess it is a matter a preference, is there any good reason to *not* do it like this? >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml >> index 0cdf53f41f84..8f414642445e 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml >> @@ -4,24 +4,26 @@ >> $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# >> $schema: http://devicetree.org/meta-schemas/core.yaml# >> >> -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 >> +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 > > Maybe just "Binding for SM8x50 SoCs" > Its likely these bindings won't be compatible with future "SM8x50" SoCs, listing supported SoCs explicitly will avoid confusion in the future. >> >> maintainers: >> - Jonathan Marek >> >> description: | >> Qualcomm display clock control module which supports the clocks, resets and >> - power domains on SM8150 and SM8250. >> + power domains on SM8150/SM8250/SM8350. > > same 8x50 comment. > >> >> See also: >> dt-bindings/clock/qcom,dispcc-sm8150.h >> dt-bindings/clock/qcom,dispcc-sm8250.h >> + dt-bindings/clock/qcom,dispcc-sm8350.h >> >> properties: >> compatible: >> enum: >> - qcom,sm8150-dispcc >> - qcom,sm8250-dispcc >> + - qcom,sm8350-dispcc >> >> clocks: >> items: >> diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h >> new file mode 120000 >> index 000000000000..0312b4544acb >> --- /dev/null >> +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h >> @@ -0,0 +1 @@ >> +qcom,dispcc-sm8250.h >> \ No newline at end of file