From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752761AbbJQLtm (ORCPT ); Sat, 17 Oct 2015 07:49:42 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:63181 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752485AbbJQLtj (ORCPT ); Sat, 17 Oct 2015 07:49:39 -0400 From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org Cc: Bharat Kumar Gogada , robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, michal.simek@xilinx.com, soren.brinkmann@xilinx.com, bhelgaas@google.com, tinamdar@apm.com, treding@nvidia.com, rjui@broadcom.com, Minghuan.Lian@freescale.com, m-karicheri2@ti.com, hauke@hauke-m.de, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Bharat Kumar Gogada , Ravi Kiran Gummaluri Subject: Re: [PATCH v4] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller Date: Sat, 17 Oct 2015 13:49:25 +0200 Message-ID: <5705956.6YyKSO4LdH@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: <1445066538-24638-1-git-send-email-bharatku@xilinx.com> References: <1445066538-24638-1-git-send-email-bharatku@xilinx.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:p3rxp0VK45jQAOsxQJt8kHZc6AyXYW8PwORC2rrGCPxaKAxpzcg IrLRX831IPjJK7v4mq9vZSVhx0d9S3oXUWNFqHWHBbu3Hu5CvzH9d8q9Br7Ra9799Ms+0t/ OowhXoRTQpe7YlM89gevEuiNfYY6HfySlnxDjglk8pblvRVyMy6O7NnRr8PO1Rs+MrWE5u2 x9CUlmiqxhs9KF+et8aug== X-UI-Out-Filterresults: notjunk:1;V01:K0:fVavAMx1ui0=:t4O0AM4yH0nBGSz/e9IhXO iU+HdpE8SLl/ylaFoJYhNvv+YtTL8JJPralmfqlyu4tizkUx+Vo0gPz/uuSUfivoIDZrw+sFb DqKgff8SgkVdjzwFbhdTAGelrVM2JH5uzfLKtPX1v6aco3xbhpASGN2RpPC4qvp+7JXOXEksB kUrfDuzh4vBQGSE9dvXMbUNOpxlg2+2sfmaPCCOlo330bQQnWx4U8Wmb8BvwVcf6ruQJCXJGg f+G23Yhm1ijisdIlfHtmKLt/B33MgV3UNQl+qwZI0qPvGupyaqSlOecNlMNORzO0vmyW2gulW u1Y+hbodx0Z2bfyS61vvkh/lULWzpeyREKt8qv4Jw0DnA79+FE69YTaCHXc81xKai2Py2YYVz 4fH/Uf5Rz84br0+ASgUvbROnGKj37xFmSbWXzHEIOS5E29pbhbFUg+GMIneiCEY9OHTzGFM74 hcD/RWycFe6LhLTVzkD5vov2gG93uuGJAkiBCgB0kl0VMDdEmwSS5rzYEatLyBxwE3c8+gJ0o kbeJdukYjTKfhxfWClBZChOF12Ilx/0oB93S4HiNTCAvjq/6LmV45Ft0YBHK0xedziNlbSYeI ZNlHTWuumya/1/w2H5ekmUtTqphCTh7qQ9QgIEWbDO+kLAQkgJTMA3spGFrN+MdTXEY9ijZ32 V0HBlyGqGoaiOab9fLy8YoDUX45i8schmtAtBEzvT7PvRIpBHGjySwhuPFftSouEAF4aK3Dku ajVkjYkL/1ZRcTXB Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Saturday 17 October 2015 12:52:18 Bharat Kumar Gogada wrote: > + "msi_1, msi_0": interrupt asserted when msi is recieved Better avoid underscores in DT, use "msi0" instead of "msi_0". > +- interrupt-map-mask and interrupt-map: standard PCI properties to define the > + mapping of the PCI interface to interrupt numbers. > +- ranges: ranges for the PCI memory regions (I/O space region is not > + supported by hardware) > + Please refer to the standard PCI bus binding document for a more > + detailed explanation > +- msi-controller: indicates that this is MSI controller node > +- msi-parent: MSI parent of the root complex itself > +- pcie_intc: Interrupt controller device node for Legacy interrupts > + - interrupt-controller: identifies the node as an interrupt controller > + - #interrupt-cells: should be set to 1 > + - #address-cells: specifies the number of cells needed to encode an > + address. The value must be 0. The name doesn't match: below, the name is "legacy-interrupt-controller", not "pcie_intc". I suppose it should really be "interrupt-controller" anyway. > + > +Example: > +++++++++ > + > +nwl_pcie: pcie@fd0e0000 { > + #address-cells = >; > + #size-cells = <2>; > + compatible = "xlnx,nwl-pcie-2.11"; > + #interrupt-cells = <1>; > + msi-controller; > + device_type = "pci"; > + interrupt-parent = <&gic>; > + interrupts = < 0 118 4 > + 0 116 4 > + 0 115 4 // MSI_1 [63...32] > + 0 114 4 >; // MSI_0 [31...0] Better write these as tuples: interrupts = <0 118 4>, <0 116 4>, <0 115 4>, <0 114 4>; And maybe reverse the order? It looks that might be what the soc integration person had in mind. Also, what is interrupt <0 117 4>? Is that connected here as well? Better list it as well then, even if you don't use it. > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1 > + 0x0 0x0 0x0 0x2 &pcie_intc 0x2 > + 0x0 0x0 0x0 0x3 &pcie_intc 0x3 > + 0x0 0x0 0x0 0x4 &pcie_intc 0x4>; > + msi-parent = <&nwl_pcie>; > + reg = <0x0 0xfd0e0000 0x1000 > + 0x0 0xfd480000 0x1000 > + 0x0 0xE0000000 0x1000000>; Same grouping for reg and interrupt-map as above for interrupts. > + reg-names = "breg", "pcireg", "cfg"; > + ranges = <0x02000000 0x00000000 0xE1000000 0x00000000 0xE1000000 0 0x0F000000>; No I/O space or prefetcheable memory? Arnd