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Wysocki" , Srinivas Kandagatla , Alberto Ruiz , Christophe Lizzi , devicetree@vger.kernel.org, Enric Balletbo , Eric Chanudet , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, NXP S32 Linux Team , Pengutronix Kernel Team , Vincent Guittot References: <20261008071436.596651-1-khristineandreea.barbulescu@oss.nxp.com> <20261008071436.596651-2-khristineandreea.barbulescu@oss.nxp.com> <20261008-1e3e0aa3fab167d544c21e68@squawk> Content-Language: en-US From: Khristine Andreea Barbulescu In-Reply-To: <20261008-1e3e0aa3fab167d544c21e68@squawk> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: FR0P281CA0261.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:b5::15) To AM9PR04MB8179.eurprd04.prod.outlook.com (2603:10a6:20b:3b5::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM9PR04MB8179:EE_|PA3PR04MB11202:EE_ X-MS-Office365-Filtering-Correlation-Id: 6293c43f-8b5c-4f77-aa9a-08df29dc2f02 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|19092799006|1800799024|366016|7416014|376014|6133799003|22082099003|18002099003|10067099003|11063799006|261009223027099003|4143699003|56012099006; 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Each EIRQ line has its own input multiplexer, >> implemented by the IMCR398-IMCR429 registers, whose Source Signal Select >> (SSS) field selects which pad signal feeds the edge detector. >> >> These registers were previously listed as reserved and were absent from >> the reg list. Add a dedicated entry for the IMCR398-IMCR429 EIRQ input >> multiplexer window between the two regular IMCR groups, update the >> example and the minimum item count for the GPIO/EIRQ variant, and drop >> IMCR398-IMCR429 from the reserved-index note. >> >> Signed-off-by: Khristine Andreea Barbulescu >> --- >> .../bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml | 9 +++++++-- >> 1 file changed, 7 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml >> index 36f2393fa406..ecf6d61a80e9 100644 >> --- a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml >> +++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml >> @@ -23,7 +23,9 @@ description: | >> are used for external interrupt configuration. >> >> Please note that some register indexes are reserved in S32G2, such as >> - MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429. >> + MSCR102-MSCR111, MSCR123-MSCR143 and IMCR84-IMCR118. IMCR398-IMCR429 >> + are not regular pin IMCRs but the EIRQ input multiplexer registers, >> + which select the pad signal routed to each external interrupt line. >> >> properties: >> compatible: >> @@ -53,6 +55,7 @@ properties: >> - description: MSCR registers group 2 in SIUL2_1 >> - description: IMCR registers group 0 in SIUL2_0 >> - description: IMCR registers group 1 in SIUL2_1 >> + - description: IMCR398-IMCR429 EIRQ input multiplexer registers in SIUL2_1 > > Isn't mid-list insertion here a compatibility break, since there's no > reg-names property here? Seems like this can just be added at the end, > without an impact on existing users? > Hi Conor, You're right. I placed it mid-list because the EIRQ window (IMCR398-IMCR429) physically sits between the two IMCR groups in the SIUL2_1 address map. But I'll move it to the end of the reg list in v2. >> - description: IMCR registers group 2 in SIUL2_1 >> - description: PGPDO registers in SIUL2_0 >> - description: PGPDI registers in SIUL2_0 >> @@ -141,7 +144,7 @@ oneOf: >> - interrupts >> properties: >> reg: >> - minItems: 11 >> + minItems: 12 > > Why is the new reg mandatory? I didn't catch the explanation for that. > > Thanks, > Conor. > The current driver just ioremaps the EIRQ region unconditionally, which is what forced the bump, but that isn't a real requirement. The EIRQ window only matters when EIRQ is used. In v2 I'll keep minItems at 11 and make the window optional: when it's absent the driver skips the EIRQ IRQ domain (already tracked via eirq_present) and EIRQ stays purely additive. Does this approach work for you? >> >> additionalProperties: false >> >> @@ -162,6 +165,8 @@ examples: >> <0x4009ca40 0x150>, >> /* IMCR119-IMCR397 registers on siul2_1 */ >> <0x44010c1c 0x45c>, >> + /* IMCR398-IMCR429 (EIRQ input mux) on siul2_1 */ >> + <0x44011078 0x80>, >> /* IMCR430-IMCR495 registers on siul2_1 */ >> <0x440110f8 0x108>, >> /* PGPDO registers on siul2_0 */ >> -- >> 2.34.1 >> On timing: I'll hold the v2 respin a bit longer. As noted in the cover letter, the series still depends on two changes that haven't landed — the rebase of 94cb9e8f2707 ("pinctrl: s32cc: implement GPIO functionality") onto the GPIO tree (currently reverted by 04b3818c3bbc) and the reg_mask_xlate alignment with 6c53312b7e2d. Until those settle the series won't apply cleanly. Regards, Khristine