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Fri, 14 Feb 2025 10:12:57 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51EACvbo004153 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 14 Feb 2025 10:12:57 GMT Received: from [10.152.195.140] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 14 Feb 2025 02:12:53 -0800 Message-ID: <57601672-2f97-4bf4-a258-4cb12ee45abc@quicinc.com> Date: Fri, 14 Feb 2025 15:42:50 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/2] arm64: dts: qcom: ipq5424: Enable PCIe PHYs and controllers To: Dmitry Baryshkov CC: , , , , , , , , , References: <20250213071912.2930066-1-quic_mmanikan@quicinc.com> <20250213071912.2930066-3-quic_mmanikan@quicinc.com> Content-Language: en-US From: Manikanta Mylavarapu In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 8sst31wenre3MX27ba_YKa0jSgAbDyuY X-Proofpoint-ORIG-GUID: 8sst31wenre3MX27ba_YKa0jSgAbDyuY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-14_04,2025-02-13_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 mlxscore=0 impostorscore=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=781 priorityscore=1501 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502140073 On 2/13/2025 6:47 PM, Dmitry Baryshkov wrote: > On Thu, Feb 13, 2025 at 12:49:12PM +0530, Manikanta Mylavarapu wrote: >> Enable the PCIe controller and PHY nodes corresponding to RDP466. >> >> Signed-off-by: Manikanta Mylavarapu >> --- >> Changes in V4: >> - Added a new line before status in pcie2 and pcie3 nodes. >> - Dropped 'output-low' property from pcie2-default-state and >> pcie3-default-state nodes. >> >> arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 41 ++++++++++++++++++++- >> 1 file changed, 40 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts >> index b6e4bb3328b3..e73f61266012 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts >> +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts >> @@ -53,6 +53,32 @@ &dwc_1 { >> dr_mode = "host"; >> }; >> >> +&pcie2 { >> + pinctrl-0 = <&pcie2_default_state>; >> + pinctrl-names = "default"; >> + >> + perst-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; > > Don't you also need wake-gpios? Here and in pcie3. > Hi Dmitry, Thank you for reviewing the patch. The wake gpio is dropped because the PCIe on the IPQ5424 doesn't support low power mode. Thanks & Regards, Manikanta.