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Fri, 27 Mar 2026 03:27:58 -0700 (PDT) Received: from [192.168.2.83] ([46.175.183.46]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48722c9f0afsm156453505e9.10.2026.03.27.03.27.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Mar 2026 03:27:57 -0700 (PDT) Message-ID: <5764b509-9d02-4d0d-afbc-8176a7c44ca1@redhat.com> Date: Fri, 27 Mar 2026 11:27:56 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next 4/5] dt-bindings: dpll: add ref-sync-sources property To: Ivan Vecera , netdev@vger.kernel.org Cc: Arkadiusz Kubalewski , Jiri Pirko , Michal Schmidt , Prathosh Satish , Simon Horman , Vadim Fedorenko , linux-kernel@vger.kernel.org, Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, Pasi Vaananen References: <20260319174826.7623-1-ivecera@redhat.com> <20260319174826.7623-5-ivecera@redhat.com> Content-Language: en-US From: Petr Oros In-Reply-To: <20260319174826.7623-5-ivecera@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit > Add ref-sync-sources phandle-array property to the dpll-pin schema > allowing board designers to declare which input pins can serve as > sync sources in a Reference-Sync pair. A Ref-Sync pair consists of > a clock reference and a low-frequency sync signal where the DPLL locks > to the clock but phase-aligns to the sync reference. > > Update both examples in the Microchip ZL3073x binding to demonstrate > the new property with a 1 PPS sync source paired to a clock source. > > Signed-off-by: Ivan Vecera > --- > .../devicetree/bindings/dpll/dpll-pin.yaml | 11 +++++++ > .../bindings/dpll/microchip,zl30731.yaml | 30 ++++++++++++++----- > 2 files changed, 34 insertions(+), 7 deletions(-) > > diff --git a/Documentation/devicetree/bindings/dpll/dpll-pin.yaml b/Documentation/devicetree/bindings/dpll/dpll-pin.yaml > index 51db93b77306f..7084f102e274c 100644 > --- a/Documentation/devicetree/bindings/dpll/dpll-pin.yaml > +++ b/Documentation/devicetree/bindings/dpll/dpll-pin.yaml > @@ -36,6 +36,17 @@ properties: > description: String exposed as the pin board label > $ref: /schemas/types.yaml#/definitions/string > > + ref-sync-sources: > + description: | > + List of phandles to input pins that can serve as the sync source > + in a Reference-Sync pair with this pin acting as the clock source. > + A Ref-Sync pair consists of a clock reference and a low-frequency > + sync signal. The DPLL locks to the clock reference but > + phase-aligns to the sync reference. > + Only valid for input pins. Each referenced pin must be a > + different input pin on the same device. > + $ref: /schemas/types.yaml#/definitions/phandle-array > + > supported-frequencies-hz: > description: List of supported frequencies for this pin, expressed in Hz. > > diff --git a/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml b/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml > index 17747f754b845..fa5a8f8e390cd 100644 > --- a/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml > +++ b/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml > @@ -52,11 +52,19 @@ examples: > #address-cells = <1>; > #size-cells = <0>; > > - pin@0 { /* REF0P */ > + sync0: pin@0 { /* REF0P - 1 PPS sync source */ > reg = <0>; > connection-type = "ext"; > - label = "Input 0"; > - supported-frequencies-hz = /bits/ 64 <1 1000>; > + label = "SMA1"; > + supported-frequencies-hz = /bits/ 64 <1>; > + }; > + > + pin@1 { /* REF0N - clock source, can pair with sync0 */ > + reg = <1>; > + connection-type = "ext"; > + label = "SMA2"; > + supported-frequencies-hz = /bits/ 64 <10000 10000000>; > + ref-sync-sources = <&sync0>; > }; > }; > > @@ -90,11 +98,19 @@ examples: > #address-cells = <1>; > #size-cells = <0>; > > - pin@0 { /* REF0P */ > + sync1: pin@0 { /* REF0P - 1 PPS sync source */ > reg = <0>; > - connection-type = "ext"; > - label = "Input 0"; > - supported-frequencies-hz = /bits/ 64 <1 1000>; > + connection-type = "gnss"; > + label = "GNSS_1PPS_IN"; > + supported-frequencies-hz = /bits/ 64 <1>; > + }; > + > + pin@1 { /* REF0N - clock source */ > + reg = <1>; > + connection-type = "gnss"; > + label = "GNSS_10M_IN"; > + supported-frequencies-hz = /bits/ 64 <10000000>; > + ref-sync-sources = <&sync1>; > }; > }; > LGTM. Reviewed-by: Petr Oros