From: Yicong Yang <yangyicong@huawei.com>
To: Junhao He <hejunhao3@huawei.com>, <will@kernel.org>,
<jonathan.cameron@huawei.com>, <linux-kernel@vger.kernel.org>,
<mark.rutland@arm.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-doc@vger.kernel.org>, <yangyicong@huawei.com>,
<shenyang39@huawei.com>, <prime.zeng@hisilicon.com>,
<yangyicong@hisilicon.com>
Subject: Re: [PATCH 3/3] docs: perf: Add new description for HiSilicon UC PMU
Date: Thu, 25 May 2023 21:41:42 +0800 [thread overview]
Message-ID: <5785e3a3-0a4d-3a75-88cf-f29f43feb6bc@huawei.com> (raw)
In-Reply-To: <20230523131825.6102-4-hejunhao3@huawei.com>
On 2023/5/23 21:18, Junhao He wrote:
> A new function is added on HiSilicon uncore UC PMU.
>
> The UC PMU support to filter statistical information based on
> the specified tx request uring channel. Make user configuration
> through "uring_channel" parameter.
> Document them to provide guidance on how to use them.
>
Since it's not a new document. Just merge this into previous patch will be better for
review.
Thanks.
> Signed-off-by: Junhao He <hejunhao3@huawei.com>
> ---
> Documentation/admin-guide/perf/hisi-pmu.rst | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/admin-guide/perf/hisi-pmu.rst b/Documentation/admin-guide/perf/hisi-pmu.rst
> index 546979360513..939a524fa1d6 100644
> --- a/Documentation/admin-guide/perf/hisi-pmu.rst
> +++ b/Documentation/admin-guide/perf/hisi-pmu.rst
> @@ -98,6 +98,14 @@ CCL/ICL-ID. For I/O die, the ICL-ID is followed by:
> 5'b00011: HAC_ICL;
> 5'b10000: PCIe_ICL;
>
> +(e) uring_channel: UC PMU events 0x47~0x59 supports filtering by tx request
> +uring channel. It is 2 bits. Some important codes are as follows:
> +2'b11: count the events which sent to the uring_ext (MATA) channel;
> +2'b01: is the same as 2'b11;
> +2'b10: count the events which sent to the uring (non-MATA) channel;
> +2'b00: default value, count the events which sent to the both uring and
> + uring_ext channel;
> +
> Users could configure IDs to count data come from specific CCL/ICL, by setting
> srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting
> tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not
>
prev parent reply other threads:[~2023-05-25 13:41 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-23 13:18 [PATCH 0/3] Add support for HiSilicon SoC uncore PMU Junhao He
2023-05-23 13:18 ` [PATCH 1/3] drivers/perf: hisi: Add support for HiSilicon H60PA and PAv3 PMU driver Junhao He
2023-05-24 4:28 ` kernel test robot
2023-05-27 8:31 ` hejunhao
2023-05-25 13:04 ` Yicong Yang
2023-05-27 9:29 ` hejunhao
2023-05-23 13:18 ` [PATCH 2/3] drivers/perf: hisi: Add support for HiSilicon UC " Junhao He
2023-05-25 13:39 ` Yicong Yang
2023-05-27 9:37 ` hejunhao
2023-05-23 13:18 ` [PATCH 3/3] docs: perf: Add new description for HiSilicon UC PMU Junhao He
2023-05-25 13:41 ` Yicong Yang [this message]
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