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> + domain-idle-states = <&cluster_sleep_pc > + &cluster_sleep_cx > + &cluster_sleep_aoss>; nit: <&foo>, <&bar>, ... (compiles to the same bytecode) [...] > + soc: soc@0 { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0 0 0 0 0x10 0>; > + dma-ranges = <0 0 0 0 0x10 0>; > + compatible = "simple-bus"; compatible should come first > + > + gcc: clock-controller@100000 { > + compatible = "qcom,sm7250-gcc"; > + reg = <0x0 0x00100000 0x0 0x1f0000>; > + clock-names = "bi_tcxo", > + "bi_tcxo_ao", > + "sleep_clk"; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&rpmhcc RPMH_CXO_CLK_A>, > + <&sleep_clk>; > + power-domains = <&rpmhpd RPMHPD_CX>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > + qupv3_id_1: geniqup@9c0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0x009c0000 0x0 0x6000>; > + clock-names = "m-ahb", "s-ahb"; > + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; I think this wrapper can be enabled globally > + > + uart2: serial@988000 { > + compatible = "qcom,geni-debug-uart"; > + reg = <0 0x00988000 0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; > + interrupts = ; > + status = "disabled"; > + }; > + }; > + > + intc: interrupt-controller@17a00000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ > + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ > + #interrupt-cells = <3>; > + interrupt-controller; > + interrupts = ; > + }; > + > + pdc: interrupt-controller@b220000 { > + compatible = "qcom,sm7250-pdc", "qcom,pdc"; > + reg = <0 0xb220000 0 0x30000>, <0 0x17c000f0 0 0x60>; > + qcom,pdc-ranges = <0 480 42>, <42 612 28>, > + <70 63 1>, <71 640 15>, <86 522 52>; 1 a line, please > + #interrupt-cells = <2>; > + interrupt-parent = <&intc>; > + interrupt-controller; > + }; > + > + spmi_bus: spmi@c440000 { > + compatible = "qcom,spmi-pmic-arb"; > + reg = <0x0 0x0c440000 0x0 0x0001100>, > + <0x0 0x0c600000 0x0 0x2000000>, > + <0x0 0x0e600000 0x0 0x0100000>, > + <0x0 0x0e700000 0x0 0x00a0000>, > + <0x0 0x0c40a000 0x0 0x0026000>; > + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; and here [...] > + apps_rsc: rsc@18200000 { > + compatible = "qcom,rpmh-rsc"; > + reg = <0x0 0x18200000 0x0 0x10000>, > + <0x0 0x18210000 0x0 0x10000>, > + <0x0 0x18220000 0x0 0x10000>; > + reg-names = "drv-0", "drv-1", "drv-2"; and here [...] > + cpufreq_hw: cpufreq@18323000 { > + compatible = "qcom,sm7250-cpufreq-hw", "qcom,cpufreq-hw"; > + reg = <0 0x18323000 0 0x1000>, > + <0 0x18325800 0 0x1000>, > + <0 0x18327800 0 0x1000>; > + reg-names = "freq-domain0", "freq-domain1", > + "freq-domain2"; and here > + > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; > + clock-names = "xo", "alternate"; > + #freq-domain-cells = <1>; > + #clock-cells = <1>; > + }; > + > + tcsr_mutex: hwlock@1f40000 { > + compatible = "qcom,tcsr-mutex"; > + reg = <0x0 0x01f40000 0x0 0x40000>; > + #hwlock-cells = <1>; > + }; > + > + timer@17c20000 { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + compatible = "arm,armv7-timer-mem"; Compatible should come as the first property > + reg = <0x0 0x17c20000 0x0 0x1000>; > + clock-frequency = <19200000>; This line should not be necessary Konrad