From: Xiaoyao Li <xiaoyao.li@intel.com>
To: Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
Adrian Hunter <adrian.hunter@intel.com>
Subject: Re: [PATCH 2/2] KVM: VMX: Allow toggling bits in MSR_IA32_RTIT_CTL when enable bit is cleared
Date: Mon, 4 Nov 2024 09:57:56 +0800 [thread overview]
Message-ID: <57e322e8-f486-4276-b9d5-4dc6c1e6e914@intel.com> (raw)
In-Reply-To: <20241101185031.1799556-3-seanjc@google.com>
On 11/2/2024 2:50 AM, Sean Christopherson wrote:
> From: Adrian Hunter <adrian.hunter@intel.com>
>
> Allow toggling other bits in MSR_IA32_RTIT_CTL if the enable bit is being
> cleared, the existing logic simply ignores the enable bit. E.g. KVM will
> incorrectly reject a write of '0' to stop tracing.
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
> Fixes: bf8c55d8dc09 ("KVM: x86: Implement Intel PT MSRs read/write emulation")
> Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
> [sean: rework changelog, drop stable@]
> Signed-off-by: Sean Christopherson <seanjc@google.com>
> ---
> arch/x86/kvm/vmx/vmx.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index 087504fb1589..9b9d115c4824 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -1636,7 +1636,8 @@ static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
> * result in a #GP unless the same write also clears TraceEn.
> */
> if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
> - ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
> + (data & RTIT_CTL_TRACEEN) &&
> + data != vmx->pt_desc.guest.ctl)
> return 1;
>
> /*
next prev parent reply other threads:[~2024-11-04 1:58 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-01 18:50 [PATCH 0/2] KVM: VMX: Mark Intel PT virtualization as BROKEN Sean Christopherson
2024-11-01 18:50 ` [PATCH 1/2] KVM: VMX: Bury Intel PT virtualization (guest/host mode) behind CONFIG_BROKEN Sean Christopherson
2024-11-04 1:56 ` Xiaoyao Li
2024-11-04 22:46 ` Sean Christopherson
2024-11-05 13:34 ` Xiaoyao Li
2024-11-04 8:23 ` Adrian Hunter
2024-11-04 23:52 ` Sean Christopherson
2024-11-08 9:07 ` Paolo Bonzini
2024-11-01 18:50 ` [PATCH 2/2] KVM: VMX: Allow toggling bits in MSR_IA32_RTIT_CTL when enable bit is cleared Sean Christopherson
2024-11-04 1:57 ` Xiaoyao Li [this message]
2024-12-19 2:41 ` [PATCH 0/2] KVM: VMX: Mark Intel PT virtualization as BROKEN Sean Christopherson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=57e322e8-f486-4276-b9d5-4dc6c1e6e914@intel.com \
--to=xiaoyao.li@intel.com \
--cc=adrian.hunter@intel.com \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=pbonzini@redhat.com \
--cc=seanjc@google.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®