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b=cR84YcGwlK3zYtqv30Hj3ZNL1ypB1wEO3/soqZKsaZQgEqIjhV4Gl4N741/SlZ8KXs2nya Y2mkjRHgAk1Pe0Cw== Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 190951379A; Fri, 9 Aug 2024 09:53:06 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id /WkwAwLntWZ0PgAAD6G6ig (envelope-from ); Fri, 09 Aug 2024 09:53:06 +0000 Message-ID: <57f11aff-95f8-41fd-b35e-a9e5a85c68e3@suse.de> Date: Fri, 9 Aug 2024 12:53:05 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 05/12] PCI: brcmstb: Use swinit reset if available To: Jim Quinlan , linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Philipp Zabel , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , open list References: <20240731222831.14895-1-james.quinlan@broadcom.com> <20240731222831.14895-6-james.quinlan@broadcom.com> Content-Language: en-US From: Stanimir Varbanov In-Reply-To: <20240731222831.14895-6-james.quinlan@broadcom.com> Content-Type: text/plain; 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DKIM_TRACE(0.00)[suse.de:+] X-Rspamd-Action: no action X-Spam-Flag: NO X-Spam-Score: -3.50 X-Rspamd-Queue-Id: 015F31F801 Hi Jim, On 8/1/24 01:28, Jim Quinlan wrote: > The 7712 SOC adds a software init reset device for the PCIe HW. > If found in the DT node, use it. > > Signed-off-by: Jim Quinlan > --- > drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index 4d68fe318178..948fd4d176bc 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -266,6 +266,7 @@ struct brcm_pcie { > struct reset_control *rescal; > struct reset_control *perst_reset; > struct reset_control *bridge_reset; > + struct reset_control *swinit_reset; > int num_memc; > u64 memc_size[PCIE_BRCM_MAX_MEMC]; > u32 hw_rev; > @@ -1633,12 +1634,30 @@ static int brcm_pcie_probe(struct platform_device *pdev) > if (IS_ERR(pcie->bridge_reset)) > return PTR_ERR(pcie->bridge_reset); > > + pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); > + if (IS_ERR(pcie->swinit_reset)) > + return PTR_ERR(pcie->swinit_reset); > + > ret = clk_prepare_enable(pcie->clk); > if (ret) > return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); > > pcie->bridge_sw_init_set(pcie, 0); > > + if (pcie->swinit_reset) { > + ret = reset_control_assert(pcie->swinit_reset); > + if (dev_err_probe(&pdev->dev, ret, "could not assert reset 'swinit'\n")) > + goto clk_disable_unprepare; > + > + /* HW team recommends 1us for proper sync and propagation of reset */ > + udelay(1); Hmm, shouldn't this delay be part of .assert/.deassert reset_control driver? I think this detail is reset-control hw specific and the consumers does not need to know it. > + > + ret = reset_control_deassert(pcie->swinit_reset); > + if (dev_err_probe(&pdev->dev, ret, > + "could not de-assert reset 'swinit' after asserting\n")) > + goto clk_disable_unprepare; > + } > + > ret = reset_control_reset(pcie->rescal); > if (dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n")) > goto clk_disable_unprepare; ~Stan