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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5c0600a4sm164839885ad.30.2026.05.19.00.46.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 May 2026 00:46:41 -0700 (PDT) Message-ID: <57f574d3-7000-42c8-a5b7-88f1a73efd50@oss.qualcomm.com> Date: Tue, 19 May 2026 15:46:36 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 05/39] drm/msm/dp: splite msm_dp_ctrl_config_ctrl() into link parts and stream parts To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> <20260410-msm-dp-mst-v4-5-b20518dea8de@oss.qualcomm.com> Content-Language: en-US From: Yongxing Mou In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Tr7WQjXh c=1 sm=1 tr=0 ts=6a0c1563 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=POr7qE6iPcSwGRG4OQYA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: E9CPRxyFag4QDu7A4G7BFsrEX6NcklL8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA3NiBTYWx0ZWRfX6Hd9C5cVwGMn TXCkKhbkWDEk1be3PlOipZ5NXsRe8gpNZJ57wYzRPo5cNJs9u0AwG+7ui5mzA2yF78BhTQ6KvxK QGyY1Aeow3pP5mLI4hQalC9SA8V62MqHXL9Vq6NDuVbcIce0PqpAmbpmXe4lXNiKvNHh+kUmCWs JeCnNAFpR/vusl/55DHaViGRWYUJCYtpF02zZujfRMs/njfBhmvIlgikt7xQlzcW64IxeNBBeP6 GEKDl2Z68nC0Aiivu+FZ6v+1ppWYLTwpZzE6qk1XjmbT09CsatowA7GpEdEcazd4p1uPmzBQUz1 5H+PTOxze605gmP5ITZERBDjueEZAOwtWjJO4/bLWfjSqfuqku+XWhd2dc5gSX0L9qJbGoJpCw8 JYthDcqEd7euxYpOxJuK1znnKioEj9VwbPJ9OsTcl3OJYF4D476rvoKI9aAIq+PmZfsfqNWFtwv fk1NNYys+M0rOnW96nw== X-Proofpoint-ORIG-GUID: E9CPRxyFag4QDu7A4G7BFsrEX6NcklL8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 bulkscore=0 malwarescore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190076 On 4/12/2026 1:34 AM, Dmitry Baryshkov wrote: > On Fri, Apr 10, 2026 at 05:33:40PM +0800, Yongxing Mou wrote: >> The DP_CONFIGURATION_CTRL register contains both link-level and >> stream-specific fields. Currently, msm_dp_ctrl_config_ctrl() configures >> all of them together. Separates the configuration into link parts and >> streams part for support MST. >> >> Signed-off-by: Yongxing Mou >> --- >> drivers/gpu/drm/msm/dp/dp_ctrl.c | 43 ++++++++++++++++++++++++++-------------- >> 1 file changed, 28 insertions(+), 15 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c >> index 476346e3ac19..85315467b5d0 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c >> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c >> @@ -388,26 +388,41 @@ void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl) >> drm_dbg_dp(ctrl->drm_dev, "mainlink off\n"); >> } >> >> -static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl) >> +static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl, >> + struct msm_dp_panel *msm_dp_panel) >> { >> u32 config = 0, tbd; >> + >> + config = msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); >> + >> + if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) >> + config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ >> + >> + tbd = msm_dp_link_get_test_bits_depth(ctrl->link, >> + msm_dp_panel->msm_dp_mode.bpp); >> + >> + config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; >> + >> + if (msm_dp_panel->psr_cap.version) >> + config |= DP_CONFIGURATION_CTRL_SEND_VSC; >> + >> + drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=0x%x\n", config); >> + >> + msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); > > You have an RMW cycle here. Please document what prevents it from racing > with the concurrent msm_dp_ctrl_config_ctrl_link(). > Here protected by mst_lock in MST case. Will add a comment. >> +} >> + >> +static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) >> +{ >> + u32 config = 0; >> const u8 *dpcd = ctrl->panel->dpcd; >> >> /* Default-> LSCLK DIV: 1/4 LCLK */ >> config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); >> >> - if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) >> - config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ >> - >> /* Scrambler reset enable */ >> if (drm_dp_alternate_scrambler_reset_cap(dpcd)) >> config |= DP_CONFIGURATION_CTRL_ASSR; >> >> - tbd = msm_dp_link_get_test_bits_depth(ctrl->link, >> - ctrl->panel->msm_dp_mode.bpp); >> - >> - config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; >> - >> /* Num of Lanes */ >> config |= ((ctrl->link->link_params.num_lanes - 1) >> << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); >> @@ -421,10 +436,7 @@ static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl) >> config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; >> config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; >> >> - if (ctrl->panel->psr_cap.version) >> - config |= DP_CONFIGURATION_CTRL_SEND_VSC; >> - >> - drm_dbg_dp(ctrl->drm_dev, "DP_CONFIGURATION_CTRL=0x%x\n", config); >> + drm_dbg_dp(ctrl->drm_dev, "link DP_CONFIGURATION_CTRL=0x%x\n", config); >> >> msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); >> } >> @@ -450,7 +462,8 @@ static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl >> msm_dp_ctrl_lane_mapping(ctrl); >> msm_dp_setup_peripheral_flush(ctrl); >> >> - msm_dp_ctrl_config_ctrl(ctrl); >> + msm_dp_ctrl_config_ctrl_link(ctrl); >> + msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); >> >> test_bits_depth = msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->panel->msm_dp_mode.bpp); >> colorimetry_cfg = msm_dp_link_get_colorimetry_config(ctrl->link); >> @@ -1628,7 +1641,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_private *ctrl, >> u8 assr; >> struct msm_dp_link_info link_info = {0}; >> >> - msm_dp_ctrl_config_ctrl(ctrl); >> + msm_dp_ctrl_config_ctrl_link(ctrl); >> >> link_info.num_lanes = ctrl->link->link_params.num_lanes; >> link_info.rate = ctrl->link->link_params.rate; >> >> -- >> 2.43.0 >> >