From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751695AbcFPG7u (ORCPT ); Thu, 16 Jun 2016 02:59:50 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:59094 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750991AbcFPG7r (ORCPT ); Thu, 16 Jun 2016 02:59:47 -0400 From: Arnd Bergmann To: Shawn Lin Cc: Bjorn Helgaas , Marc Zyngier , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Heiko Stuebner , Doug Anderson , Wenrui Li , Rob Herring , devicetree@vger.kernel.org, Thomas Petazzoni Subject: Re: [PATCH v3 1/2] Documentation: bindings: add dt doc for Rockchip PCIe controller Date: Thu, 16 Jun 2016 09:00:41 +0200 Message-ID: <5811436.gqkV56Lax5@wuerfel> User-Agent: KMail/5.1.3 (Linux/4.4.0-22-generic; KDE/5.18.0; x86_64; ; ) In-Reply-To: <1466041821-1649-1-git-send-email-shawn.lin@rock-chips.com> References: <1466041821-1649-1-git-send-email-shawn.lin@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:2GD9Wwzy8W9A0R4qLODzKTBzSOBFzZ5bujjVfkz+spOqiim3Yx6 OS802WrzKi2nwbDc2DZvruASnKL2EGjrKjR2dMqsyAUwmPQ197DIlodv/48tXxrDBt17LXJ Gvu5U/W5Dx3zhiDv9IvEuEPHbL+f6ZTuR9JtiRfV8WtZDoLgyIk2UFBcIQ8WPS4VJvh53ze W++Z2v6FFtU7LLgfhSyMQ== X-UI-Out-Filterresults: notjunk:1;V01:K0:xtsUaEayBKo=:pwm9/bAwFdhnXEsOaVeByF QLYW0HqPbSBv30eZuCbgAy9h0+1MNQsLpn0Mc4uOVtNUPWQWIGY83NC9IpAgcv6z3/fmA8nTm QxucgzuPfesLDdUE9IYUvraTY36kb8/BQfx5nNghj9/ByqrgUxrgV1cfeYpQnFhMFRw3d7BrC Tht2O2+ZFg8r2VX85KZEedE/c9TVWIchh3avhS1IhMNLl9iUhOj4GAJ5TAwD8q1py58WmBOfI FeEqZEqQdDsgwx8VZCkZfvx5fjg7uT7qIZFKpYJWWC3ls3DhpMRQQEpsQlSnPHqUF+WFI6c1l T6aW4jfh+oQiPmzQ0Pq2ihcRkLXp9VtdJKwwFXUscLL4v3ri0sZOZh9s6N8PP4CA1qhwbdVMA q6J5XqBBqUTqewVPSMlJM8hKktVLnUzx8l2foTxPzHBU15t4Hsw8wxXERq6wul9RUn8EmhsZ+ RsfsZ8Y4ajLR4lAHYQJbECICfBYNQDq6kZwqzJv5cBFbSCapvHrudBUj/LXWR5V8pCgdEz80d Z8E7UTrU9G0zMQl6zqBIGX++4Bf5qLbjKUmaXOGQ1HFMRWxp0nXu/+d1RIt3lMdJXvjcs2BQ8 hDZz3iirP0hXyktwwSgcqP4nPhDciZCXru7zHzG2dPY3ROs9U3qX692r/6LfbRwbXAeoc9Rv+ c3Uq1UDVPFFH6ACy79FUOJTKISs493Tsy0TbJMOCBCizrbhYv70nHAwm95mk8jLnKZyoBL2BA rJCLxmKmuRaBaEA9 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thursday, June 16, 2016 9:50:21 AM CEST Shawn Lin wrote: > + reset-names = "core", "mgmt", "mgmt-sticky", "pipe"; > + phys = <&pcie_phy>; > + phy-names = "pcie-phy"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie_clkreq>; > + #interrupt-cells = <1>; > + interrupt-controller; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie0 1>, > + <0 0 0 2 &pcie0 2>, > + <0 0 0 3 &pcie0 3>, > + <0 0 0 4 &pcie0 4>; > +}; > One thing that came up in the review of the new Marvell PCIe driver is that it's most likely invalid for a device node to have both "interrupt-controller" and "interrupt-map" properties. I originally thought this was a nice way to handle embedded irqchips within the PCIe host, but it only really works by coincidence with the current kernel, and only as long as the hwirq number of the irqchip matches the integer representation of the irq line in the root bridge (which it does in the example above). For that driver we concluded that it would be less of a hack to have the irqchip as a child node of the PCIe host after all (just not with device_type="pci" of course), and that makes the translation work as expected. Arnd