From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55404C433EF for ; Fri, 8 Jul 2022 15:42:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238366AbiGHPmh (ORCPT ); Fri, 8 Jul 2022 11:42:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232582AbiGHPmf (ORCPT ); Fri, 8 Jul 2022 11:42:35 -0400 Received: from mail-il1-x130.google.com (mail-il1-x130.google.com [IPv6:2607:f8b0:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC48B61D6C; Fri, 8 Jul 2022 08:42:34 -0700 (PDT) Received: by mail-il1-x130.google.com with SMTP id m14so10286427iln.10; Fri, 08 Jul 2022 08:42:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=1qbexzS6sol5qJ39FyR4R0bbeTrcJijBH7KTqUd0Ou8=; b=SwjJ9VYJLFyQCQJDmktrB+p9IemrszRWS/6xHtGftz6bTaFQ60Ai5c/vhHvJ/HoYpj x3DMyzXOy9AC+leTEXpHVf/JhsvZXoT0LCbRNrd7Unk/gWj/gNmcCQoqZHGasCcEN8SH Bn7psIeduhzabFb9TecVtcYFsBKumv3iG00LabLyDU1dmJWUXDU3xkF7ChFDMuyHTSip hrkRrBmh2iqJDFN7RIEQqEPY9ZJIhE2qKqWrJaTjIQX9JLTTq2iW6gRKgmD6pC9V4yif 02nApBb+hbZLzP+h2lomwhGm9NWEki3RDudjL8QcW1RysgIlKk0mL1TT2IgnNpXChR+D dgRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=1qbexzS6sol5qJ39FyR4R0bbeTrcJijBH7KTqUd0Ou8=; b=CynS+fWXbw68fLKjNeH5KfDziX9gHBJ3jpfcpOQ8/QkBOAVqOMsaIDo981GFguk+GG Wq+FlyPFXTICXsD5E2qEQcvY+hOyLMGaMpCrOVm+bbuQ5yrm6NmH2cKeLciofXVv7XwJ fn792w26bPK5Ag3+vu+VRSlzTQUV4rEQWAcISMjdnofw8R0TEclaoO+aIkwFiiLqcA6g 0XgFcG01z6BLN1OAg2LZ3gSDzVRetgo+om4TKI8U8+v2J21B/1KvJK88QtMU1lmPRt06 48NQcxnouZy4LXLNDtOgddkE/GIoBbZWdPvGHGIBdr7v0iEsmaU8x4q1CoyS65jn3721 Pr7Q== X-Gm-Message-State: AJIora/VFF19f0gZpA6f5/nrZMzxEewnPXTrcMsFf4kyL78pURud09xh GHLMtSIO1Acdpz8RwKYwWKc= X-Google-Smtp-Source: AGRyM1vz8B/CoTAGqci2yIFVCBapyRIex1680cllaQQhyX5o64k7/OZUGHA80vWS9TD2sV6E27bDfA== X-Received: by 2002:a05:6e02:174a:b0:2da:c72f:e3a6 with SMTP id y10-20020a056e02174a00b002dac72fe3a6mr2446019ill.309.1657294954008; Fri, 08 Jul 2022 08:42:34 -0700 (PDT) Received: from [192.168.1.145] ([207.188.167.132]) by smtp.gmail.com with ESMTPSA id a9-20020a92c709000000b002dc133c9468sm5698548ilp.6.2022.07.08.08.42.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Jul 2022 08:42:32 -0700 (PDT) Message-ID: <5841cdea-2587-5bd8-3e6c-19e49121677a@gmail.com> Date: Fri, 8 Jul 2022 17:42:28 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v24 07/10] soc: mediatek: mmsys: add mmsys for support 64 reset bits Content-Language: en-US To: "Nancy.Lin" , Rob Herring , Chun-Kuang Hu , Philipp Zabel , wim@linux-watchdog.org, AngeloGioacchino Del Regno , linux@roeck-us.net Cc: David Airlie , Daniel Vetter , Nathan Chancellor , Nick Desaulniers , "jason-jh . lin" , Yongqiang Niu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org, llvm@lists.linux.dev, singo.chang@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com References: <20220622130824.29143-1-nancy.lin@mediatek.com> <20220622130824.29143-8-nancy.lin@mediatek.com> From: Matthias Brugger In-Reply-To: <20220622130824.29143-8-nancy.lin@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 22/06/2022 15:08, Nancy.Lin wrote: > Add mmsys for support 64 reset bits. It is a preparation for MT8195 > vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset bits. > > 1. Add the number of reset bits in mmsys private data > 2. move the whole "reset register code section" behind the > "get mmsys->data" code section for getting the num_resets in mmsys->data. > > Signed-off-by: Nancy.Lin > Reviewed-by: AngeloGioacchino Del Regno > Reviewed-by: CK Hu > Tested-by: Bo-Chen Chen > --- > drivers/soc/mediatek/mtk-mmsys.c | 35 ++++++++++++++++++++------------ > drivers/soc/mediatek/mtk-mmsys.h | 1 + > 2 files changed, 23 insertions(+), 13 deletions(-) > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 16be77d5acac..47b72ae72cc2 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -20,6 +20,8 @@ > #include "mt8195-mmsys.h" > #include "mt8365-mmsys.h" > > +#define MMSYS_SW_RESET_PER_REG 32 > + > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .clk_driver = "clk-mt2701-mm", > .routes = mmsys_default_routing_table, > @@ -86,6 +88,7 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > .routes = mmsys_default_routing_table, > .num_routes = ARRAY_SIZE(mmsys_default_routing_table), > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, > + .num_resets = 32, > }; > > static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = { > @@ -100,6 +103,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .routes = mmsys_mt8183_routing_table, > .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, > + .num_resets = 32, > }; > > static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = { > @@ -114,6 +118,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { > .routes = mmsys_mt8186_routing_table, > .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table), > .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, > + .num_resets = 32, > }; > > static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = { > @@ -288,10 +293,14 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l > { > struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev); > unsigned long flags; > + u32 offset; > + > + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); > + id = id % MMSYS_SW_RESET_PER_REG; > > spin_lock_irqsave(&mmsys->lock, flags); > > - mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), > + mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset + offset, BIT(id), > assert ? 0 : BIT(id), NULL); reg = mmsys->data->sw0_rst_offset + offset; mtk_mmsys_update_bits(mmsys, reg, BIT(id), assert ? 0 : BIT(id), NULL); Other then that, patch looks good. By the way setting val depending on assert in the function call gets (for me) hard to read, as I said earlier. Regards, Matthias > > spin_unlock_irqrestore(&mmsys->lock, flags); > @@ -349,18 +358,6 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > return ret; > } > > - spin_lock_init(&mmsys->lock); > - > - mmsys->rcdev.owner = THIS_MODULE; > - mmsys->rcdev.nr_resets = 32; > - mmsys->rcdev.ops = &mtk_mmsys_reset_ops; > - mmsys->rcdev.of_node = pdev->dev.of_node; > - ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); > - if (ret) { > - dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret); > - return ret; > - } > - > res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > if (!res) { > dev_err(dev, "Couldn't get mmsys resource\n"); > @@ -382,6 +379,18 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > mmsys->data = match_data->drv_data[0]; > } > > + spin_lock_init(&mmsys->lock); > + > + mmsys->rcdev.owner = THIS_MODULE; > + mmsys->rcdev.nr_resets = mmsys->data->num_resets; > + mmsys->rcdev.ops = &mtk_mmsys_reset_ops; > + mmsys->rcdev.of_node = pdev->dev.of_node; > + ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); > + if (ret) { > + dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret); > + return ret; > + } > + > #if IS_REACHABLE(CONFIG_MTK_CMDQ) > ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); > if (ret) > diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h > index f01ba206481d..20a271b80b3b 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.h > +++ b/drivers/soc/mediatek/mtk-mmsys.h > @@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data { > const struct mtk_mmsys_routes *routes; > const unsigned int num_routes; > const u16 sw0_rst_offset; > + const u32 num_resets; > }; > > struct mtk_mmsys_match_data {