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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b76f59a6a67sm172720266b.34.2025.11.27.06.25.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Nov 2025 06:25:29 -0800 (PST) Message-ID: <58570d98-f8f1-4e8c-8ae2-5f70a1ced67a@oss.qualcomm.com> Date: Thu, 27 Nov 2025 15:25:27 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/msm: Fix a7xx per pipe register programming To: Anna Maniscalco , Rob Clark , Sean Paul , Konrad Dybcio , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Antonino Maniscalco Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20251127-gras_nc_mode_fix-v1-1-5c0cf616401f@gmail.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20251127-gras_nc_mode_fix-v1-1-5c0cf616401f@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI3MDEwNyBTYWx0ZWRfX8QOI0U2OrqTy tDCSeJhrA62CqnqTs9aIeFyPBbPoVoKDl3+Nr0yxAEkNbg8Z4QJymOTtKeb+meRvu8NGdVoc5oC FJB2rHqU5EC3tpA3kSXKM8Sn7xNrUglhWkJq7v4hUhQqdM6WaRXVYSNJ238q5VsT8zTxcU/AIAL avi9uS6FhxKOa3kWZR8TUKMvgXeVzlrI3blcl6nyefrvbEmslkjFbKXpRoEP7j3lfpCC9riwG4y 4SlFVO5NZ5QLwU6Z5nnQH3k9Ca3hGfojPbYO3kwJLVKHekN6G21wqNdd6KjR83s7VCyxDiOJ/EJ id1A/mcY+atCqYPxne7aL+nN9cevj6ie8Jrdjb/8HzIrqGsft/Uw0eaxos9ekmQNASgkXt+upNf cBWQlFyPb7vmPx316yCqR/eEyKjouQ== X-Proofpoint-GUID: 6wFnFXUsDpf58nqziYqHcV4XXW3_-9lz X-Proofpoint-ORIG-GUID: 6wFnFXUsDpf58nqziYqHcV4XXW3_-9lz X-Authority-Analysis: v=2.4 cv=PJoCOPqC c=1 sm=1 tr=0 ts=69285f5c cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=pGLkceISAAAA:8 a=51bRkEKeLUuq6sK2_JkA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_02,2025-11-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 priorityscore=1501 clxscore=1015 adultscore=0 impostorscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511270107 On 11/27/25 12:46 AM, Anna Maniscalco wrote: > GEN7_GRAS_NC_MODE_CNTL was only programmed for BR and not for BV pipe > but it needs to be programmed for both. > > Program both pipes in hw_init and introducea separate reglist for it in > order to add this register to the dynamic reglist which supports > restoring registers per pipe. > > Fixes: 91389b4e3263 ("drm/msm/a6xx: Add a pwrup_list field to a6xx_info") > Signed-off-by: Anna Maniscalco > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 9 ++- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 91 +++++++++++++++++++++++++++++-- > drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 13 +++++ > 4 files changed, 109 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index 29107b362346..c8d0b1d59b68 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -1376,7 +1376,6 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = { > REG_A6XX_UCHE_MODE_CNTL, > REG_A6XX_RB_NC_MODE_CNTL, > REG_A6XX_RB_CMP_DBG_ECO_CNTL, > - REG_A7XX_GRAS_NC_MODE_CNTL, > REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, > REG_A6XX_UCHE_GBIF_GX_CONFIG, > REG_A6XX_UCHE_CLIENT_PF, > @@ -1448,6 +1447,12 @@ static const u32 a750_ifpc_reglist_regs[] = { > > DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist); > > +static const struct adreno_reglist_pipe a750_reglist_pipe_regs[] = { > + { REG_A7XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, At a glance at kgsl, all gen7 GPUs that support concurrent binning (i.e. not gen7_3_0/a710? and gen7_14_0/whatever that translates to) need this Konrad