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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2aba87d7b9dsm62424812eec.4.2025.12.09.15.44.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Dec 2025 15:44:24 -0800 (PST) Message-ID: <586da917-6ea6-4b99-8222-7c49a5452451@oss.qualcomm.com> Date: Tue, 9 Dec 2025 15:44:23 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 8/9] phy: qualcomm: qmp-combo: Update QMP PHY with Glymur settings To: Dmitry Baryshkov Cc: krzk+dt@kernel.org, abel.vesa@linaro.org, conor+dt@kernel.org, vkoul@kernel.org, robh@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251209-linux-next-12825-v8-0-42133596bda0@oss.qualcomm.com> <20251209-linux-next-12825-v8-8-42133596bda0@oss.qualcomm.com> <4f3og44prqjjxsiy5lwnxam3ikqylvmk3m2ofsxoa5byczhs56@3uvxjtobddxf> Content-Language: en-US From: Wesley Cheng In-Reply-To: <4f3og44prqjjxsiy5lwnxam3ikqylvmk3m2ofsxoa5byczhs56@3uvxjtobddxf> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA5MDE4NiBTYWx0ZWRfXyvdzET7OGR6Z 9PLz3xt8gtLZcqAkgHWollBZ+l5yWUb1mHn+CyXBmpN7EJLYA77bMm/IUpUwSlI2zi0jcBz6Ccm PrdyPrhIOqM79zGa0G/64Tvnwmyc8DHeYc5JC9arKoSVNB6dArQWBfYF8Qf0eCP5jQQnCFznhqk U1TvriIkZ4a4kURcW/R1pWG64Hb9XIqV8tXJO8i6NDD7pewzpUVwHS5vmgCi64/CDNFYrUDuMKb 0xag3iIPBZeuxWmLlFzPUUunJFenHeSmSQFCf0GlyVaTiZFxC4KqcOdDnhCXVJBVDAyIMweW67H jl4aauikKtsC+LRkB/eOPShGwM/RwHYPSglkK6qaP0iK2hd750uIMZdjKUnKK0qUGqDkq4py4o2 N8I6FsjhjIV36ZIBotZ3R0FcITtxrQ== X-Proofpoint-ORIG-GUID: D8YzLviXRql5WO9uJtpj49L-813iFpye X-Authority-Analysis: v=2.4 cv=Vcj6/Vp9 c=1 sm=1 tr=0 ts=6938b45b cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=GfICSpz_d4rxbVQ3OkEA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-GUID: D8YzLviXRql5WO9uJtpj49L-813iFpye X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-09_05,2025-12-09_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 malwarescore=0 impostorscore=0 suspectscore=0 adultscore=0 priorityscore=1501 bulkscore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512090186 On 12/9/2025 3:19 PM, Dmitry Baryshkov wrote: > On Tue, Dec 09, 2025 at 03:09:44PM -0800, Wesley Cheng wrote: >> For SuperSpeed USB to work properly, there is a set of HW settings that >> need to be programmed into the USB blocks within the QMP PHY. Ensure that >> these settings follow the latest settings mentioned in the HW programming >> guide. The QMP USB PHY on Glymur is a USB43 based PHY that will have some >> new ways to define certain registers, such as the replacement of TXA/RXA >> and TXB/RXB register sets. This was replaced with the LALB register set. >> >> There are also some PHY init updates to modify the PCS MISC register space. >> Without these, the QMP PHY PLL locking fails. >> >> Signed-off-by: Wesley Cheng >> --- >> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 285 +++++++++ >> drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v8.h | 17 + >> drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v8.h | 12 + >> .../phy/qualcomm/phy-qcom-qmp-qserdes-lalb-v8.h | 639 +++++++++++++++++++++ >> drivers/phy/qualcomm/phy-qcom-qmp-usb43-pcs-v8.h | 33 ++ >> .../qualcomm/phy-qcom-qmp-usb43-qserdes-com-v8.h | 224 ++++++++ >> drivers/phy/qualcomm/phy-qcom-qmp.h | 2 + >> 7 files changed, 1212 insertions(+) >> > > Does this work without DP tables? > Hi Dmitry, Yes, it works without DP settings. I verified it on v7 before sending it upstream, which did not include the DP tables. On this series, I verified that the QMP DP block is initialized properly on top of the existing support for USB3. Thanks Wesley Cheng