From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750742AbdAWGNG (ORCPT ); Mon, 23 Jan 2017 01:13:06 -0500 Received: from regular1.263xmail.com ([211.150.99.130]:53206 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750703AbdAWGNF (ORCPT ); Mon, 23 Jan 2017 01:13:05 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: zyw@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zyw@rock-chips.com X-UNIQUE-TAG: <6fda83fe72e0ac4dd121c737867f8f96> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH v2 25/26] drm/rockchip: dw-mipi-dsi: add reset control To: John Keeping , Mark Yao References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-26-john@metanate.com> Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org From: Chris Zhong Message-ID: <58859EEA.7080309@rock-chips.com> Date: Mon, 23 Jan 2017 14:12:58 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <20170121163128.22240-26-john@metanate.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Reviewed-by: Chris Zhong On 01/22/2017 12:31 AM, John Keeping wrote: > In order to fully reset the state of the MIPI controller we must assert > this reset. > > This is slightly more complicated than it could be in order to maintain > compatibility with device trees that do not specify the reset property. > > Signed-off-by: John Keeping > --- > Unchanged in v2 > --- > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index 881bb0c62ca5..f780401e8b5e 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -13,6 +13,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -1121,6 +1122,7 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, > of_match_device(dw_mipi_dsi_dt_ids, dev); > const struct dw_mipi_dsi_plat_data *pdata = of_id->data; > struct platform_device *pdev = to_platform_device(dev); > + struct reset_control *apb_rst; > struct drm_device *drm = data; > struct dw_mipi_dsi *dsi; > struct resource *res; > @@ -1159,6 +1161,34 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, > return ret; > } > > + /* > + * Note that the reset was not defined in the initial device tree, so > + * we have to be prepared for it not being found. > + */ > + apb_rst = devm_reset_control_get(dev, "apb"); > + if (IS_ERR(apb_rst)) { > + if (PTR_ERR(apb_rst) == -ENODEV) { > + apb_rst = NULL; > + } else { > + dev_err(dev, "Unable to get reset control: %d\n", ret); > + return PTR_ERR(apb_rst); > + } > + } > + > + if (apb_rst) { > + ret = clk_prepare_enable(dsi->pclk); > + if (ret) { > + dev_err(dev, "%s: Failed to enable pclk\n", __func__); > + return ret; > + } > + > + reset_control_assert(apb_rst); > + usleep_range(10, 20); > + reset_control_deassert(apb_rst); > + > + clk_disable_unprepare(dsi->pclk); > + } > + > ret = clk_prepare_enable(dsi->pllref_clk); > if (ret) { > dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);