From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1F44C4727E for ; Wed, 30 Sep 2020 14:37:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 804EB206D4 for ; Wed, 30 Sep 2020 14:37:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="E4pQQ9Ae" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730620AbgI3Ohv (ORCPT ); Wed, 30 Sep 2020 10:37:51 -0400 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:49368 "EHLO us-smtp-delivery-124.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728149AbgI3Ohv (ORCPT ); Wed, 30 Sep 2020 10:37:51 -0400 Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1601476670; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gvcoPWLZ/UXHXFLFR/AWxZXN9OnxSpqvTsQKFwNAyGQ=; b=E4pQQ9AeIQxkH3s4GvX3H6/lmpmTJayc0qW3q83jdcuNy2J8JS1fvqaCmluOQpbtIXkK0L y3W+hw3CPyhr5EbCUaWY3VGdh+dsgWo9OJZIyLUsthPOQHOJ4ieqvz4uq0OobVdJg0qn7D yRsTvqZveqmzkGRkPIf9pnG9Lx7jlLA= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-272-CBQgIOVjPnW1gt4xLqZ1UQ-1; Wed, 30 Sep 2020 10:37:47 -0400 X-MC-Unique: CBQgIOVjPnW1gt4xLqZ1UQ-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id F3AD785C732; Wed, 30 Sep 2020 14:37:45 +0000 (UTC) Received: from starship (unknown [10.35.206.29]) by smtp.corp.redhat.com (Postfix) with ESMTP id 202E05579D; Wed, 30 Sep 2020 14:37:41 +0000 (UTC) Message-ID: <58b7aa949cbdfefbb6149608ac0f45c8b25d5640.camel@redhat.com> Subject: Re: [PATCH v2 1/1] KVM: x86: fix MSR_IA32_TSC read for nested migration From: Maxim Levitsky To: Paolo Bonzini , kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Jim Mattson , Wanpeng Li , Ingo Molnar , Sean Christopherson , Borislav Petkov , Thomas Gleixner , Vitaly Kuznetsov , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , Joerg Roedel , "H. Peter Anvin" Date: Wed, 30 Sep 2020 17:37:41 +0300 In-Reply-To: References: <20200921103805.9102-1-mlevitsk@redhat.com> <20200921103805.9102-2-mlevitsk@redhat.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.36.3 (3.36.3-1.fc32) MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2020-09-24 at 19:33 +0200, Paolo Bonzini wrote: > On 21/09/20 12:38, Maxim Levitsky wrote: > > MSR reads/writes should always access the L1 state, since the (nested) > > hypervisor should intercept all the msrs it wants to adjust, and these > > that it doesn't should be read by the guest as if the host had read it. > > > > However IA32_TSC is an exception. Even when not intercepted, guest still > > reads the value + TSC offset. > > The write however does not take any TSC offset into account. > > > > This is documented in Intel's SDM and seems also to happen on AMD as well. > > > > This creates a problem when userspace wants to read the IA32_TSC value and then > > write it. (e.g for migration) > > > > In this case it reads L2 value but write is interpreted as an L1 value. > > To fix this make the userspace initiated reads of IA32_TSC return L1 value > > as well. > > > > Huge thanks to Dave Gilbert for helping me understand this very confusing > > semantic of MSR writes. > > > > Signed-off-by: Maxim Levitsky > > --- > > arch/x86/kvm/x86.c | 16 ++++++++++++++-- > > 1 file changed, 14 insertions(+), 2 deletions(-) > > > > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > > index 17f4995e80a7e..ed4314641360e 100644 > > --- a/arch/x86/kvm/x86.c > > +++ b/arch/x86/kvm/x86.c > > @@ -3219,9 +3219,21 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > > case MSR_IA32_POWER_CTL: > > msr_info->data = vcpu->arch.msr_ia32_power_ctl; > > break; > > - case MSR_IA32_TSC: > > - msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset; > > + case MSR_IA32_TSC: { > > + /* > > + * Intel SDM states that MSR_IA32_TSC read adds the TSC offset > > + * even when not intercepted. AMD manual doesn't explicitly > > + * state this but appears to behave the same. > > + * > > + * However when userspace wants to read this MSR, we should > > + * return it's real L1 value so that its restore will be correct. > > + */ > > + u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset : > > + vcpu->arch.tsc_offset; > > + > > + msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset; > > break; > > + } > > case MSR_MTRRcap: > > case 0x200 ... 0x2ff: > > return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); > > > > Applied the patch as it is doing the sanest possible thing for the > current semantics of host-initiated accesses. > > Paolo > Thanks! Best regards, Maxim Levitsky