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charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=c4g+0h9l c=1 sm=1 tr=0 ts=6aa4e46b cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=Q/e3f29T3Hw2hnAEzBPF7w==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=F_M2Yv-rfSBzxpAF3TcA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTEyMDA3NyBTYWx0ZWRfXx/0IRzj2jesl A0vn9W+jPl0TpTjh254PT16P8bnrwPZkJFW6ocoyBTrErbQcWqqedUE37JAQG1ZVgPH4gNjM8mD vyJKKRmDDBJZ89VbE/CYtfEQ0JeHsvY= X-Proofpoint-GUID: 4wH-j-JvS7U2OyNxu-KcnMjspg_FSTXw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTEyMDA3NyBTYWx0ZWRfX/KOe5JFfAkj2 4Q0BEcM1U6621r+lCnNsFDFNs0MOUp+Bf1Mo5xXtuKwVWec7E9gul4wosh5tU8+LMWQzDk2n7qI ixOIGVydo9Y2CT6N5COvQ2o4QrTjXZLU02PqY9crRMTSnoOiexPVhfo4f3TRwWoCvtaAuKkkXD7 YV3EbXEekgNI+G4XpeJZCI5e93ntXHPUyVUcMAQM6bojLhIkTZUCb2Pg9ocycQdouCNbmrHNNeM pzMqsZ/PBg+zgUySCQopFL6snYRU6hjW2AsRtCEayFVnxsktBpmC+fvX72tPYB5cKxjMZpYjC7D 3t2B3lxtewi5BIOf2HMGJ0oww4xIAs4P7VdBon7vQOXDDS9rJleR55EdkYrNfOaA7D9pwMLYndH 51rZsdBQl3SE6jcU0SgnI24yrYy3DEHJKVV1OaSyYFgB91mtD4zWD+mkpOHxseqWQ1jS4t6GFey w6ckE8gedNHDSOOQY+Q== X-Proofpoint-ORIG-GUID: 4wH-j-JvS7U2OyNxu-KcnMjspg_FSTXw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-12_02,2026-09-11_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 adultscore=0 bulkscore=0 impostorscore=0 malwarescore=0 phishscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609120077 On 9/11/2026 5:17 PM, Gjorgji Rosikopulos (Consultant) wrote: > Hi Loic, > > Thanks for the review, > > On 9/11/2026 4:30 PM, Loic Poulain wrote: >> Hi Gjorgji, >> >> On Fri, Sep 11, 2026 at 8:22 AM Gjorgji Rosikopulos >> wrote: >>> >>> From: Gjorgji Rosikopulos >>> >>> Implement the configure_rx/enable_stream/disable_stream hw_ops added to >>> struct csid_hw_ops, for the gen2 CSID hardware backend used by SM8250. >>> >>> __csid_configure_rdi_stream() now takes an explicit data type parameter >>> instead of deriving it from the CSID source pad's format, since the >>> streams API keys each stream by stream_id rather than by pad. The >>> existing configure_stream() path is updated to pass its per-port format >>> lookup through to this parameter, preserving current behavior. >>> >>> Signed-off-by: Gjorgji Rosikopulos >>> --- >>> .../platform/qcom/camss/camss-csid-gen2.c | 59 ++++++++++++++++--- >>> 1 file changed, 51 insertions(+), 8 deletions(-) >>> >>> diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/media/platform/qcom/camss/camss-csid-gen2.c >>> index eadcb2f7e3aa..2512cdb16d94 100644 >>> --- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c >>> +++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c >>> @@ -253,13 +253,8 @@ static void __csid_configure_testgen(struct csid_device *csid, u8 enable, u8 por >>> writel_relaxed(val, csid->base + CSID_TPG_CTRL); >>> } >>> >>> -static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 port, u8 vc) >>> +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 port, u8 vc, u8 dt) >>> { >>> - /* Source pads matching RDI channels on hardware. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. */ >>> - struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + port]; >>> - const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats, >>> - csid->res->formats->nformats, >>> - input_format->code); >>> u32 val; >>> >>> /* >>> @@ -281,7 +276,7 @@ static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 >>> val |= 1 << RDI_CFG0_TIMESTAMP_EN; >>> /* note: for non-RDI path, this should be format->decode_format */ >>> val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; >>> - val |= format->data_type << RDI_CFG0_DATA_TYPE; >>> + val |= dt << RDI_CFG0_DATA_TYPE; >>> val |= vc << RDI_CFG0_VIRTUAL_CHANNEL; >>> val |= dt_id << RDI_CFG0_DT_ID; >>> writel_relaxed(val, csid->base + CSID_RDI_CFG0(port)); >>> @@ -330,15 +325,60 @@ static void csid_configure_stream(struct csid_device *csid, u8 enable) >>> /* Loop through all enabled ports and configure a stream for each */ >>> for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++) >>> if (csid->phy.en_vc & BIT(i)) { >>> + /* Source pads match RDI channels: pad 1 -> RDI0, pad 2 -> RDI1, etc. */ >>> + struct v4l2_mbus_framefmt *input_format = >>> + &csid->fmt[MSM_CSID_PAD_FIRST_SRC + i]; >>> + const struct csid_format_info *format = >>> + csid_get_fmt_entry(csid->res->formats->formats, >>> + csid->res->formats->nformats, >>> + input_format->code); >>> + u8 vc = 0; >>> + >>> if (tg->enabled) >>> __csid_configure_testgen(csid, enable, i, 0); >>> >>> - __csid_configure_rdi_stream(csid, enable, i, 0); >>> + __csid_configure_rdi_stream(csid, enable, i, vc, format->data_type); >>> __csid_configure_rx(csid, &csid->phy, 0); >>> __csid_ctrl_rdi(csid, enable, i); >>> } >>> } >>> >>> +/* >>> + * configure_rx - Configure the CSID Rx front-end >>> + */ >>> +static void csid_configure_rx(struct csid_device *csid) >>> +{ >>> + __csid_configure_rx(csid, &csid->phy, 0); >>> +} >>> + >>> +/* >>> + * stream_id is used directly as the hardware RDI port index below. This >>> + * assumes a 1:1 stream-to-port mapping and should be revisited once >>> + * per-platform src_streams data (stream id -> hw pipe) is added. >>> + */ >>> +static void csid_enable_stream(struct csid_device *csid, u32 stream_id, u8 vc, u8 dt) >>> +{ >>> + struct csid_testgen_config *tg = &csid->testgen; >>> + >>> + if (tg->enabled) >>> + __csid_configure_testgen(csid, 1, stream_id, vc); >>> + >>> + __csid_configure_rdi_stream(csid, 1, stream_id, vc, dt); >>> + __csid_ctrl_rdi(csid, 1, stream_id); >>> +} >>> + >>> +static void csid_disable_stream(struct csid_device *csid, u32 stream_id) >>> +{ >>> + struct csid_testgen_config *tg = &csid->testgen; >>> + >>> + __csid_ctrl_rdi(csid, 0, stream_id); >>> + >>> + if (tg->enabled) >>> + __csid_configure_testgen(csid, 0, stream_id, 0); >>> + >>> + __csid_configure_rdi_stream(csid, 0, stream_id, 0, 0); >>> +} >>> + >>> static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val) >>> { >>> if (val > 0 && val <= csid->testgen.nmodes) >>> @@ -425,6 +465,9 @@ static void csid_subdev_init(struct csid_device *csid) >>> const struct csid_hw_ops csid_ops_gen2 = { >>> .configure_stream = csid_configure_stream, >>> .configure_testgen_pattern = csid_configure_testgen_pattern, >>> + .configure_rx = csid_configure_rx, >>> + .enable_stream = csid_enable_stream, >>> + .disable_stream = csid_disable_stream, >> >> Would it be possible to leverage the existing CSID configure_stream() >> callback to implement the stream API? This would likely require >> reconfiguring all CSID ports whenever a stream is started/stopped, but >> if the configuration remains unchanged, I do not think that would be >> problematic. That said, we probably need to address the current >> ambiguity between the concepts of "VC" and "PORT" in the existing >> drivers first. > > I have experimented with something similar, we know in advance which > streams will be routed and active using stream routes, we can enable > them in advance. The drawback of that was that all the streams (even inactive) > will be enabled when first stream is enabled, but that is the case even today. > > What you propose is something different, but that will require changing of the existing > api and verification of all csid implementations, i am ok with the proposal > if someone can help with the verification of other devices. In addition using configure_stream and one api for multiple streams will make the interface more complex. We need to extend the interface with stream id's and pass vc/dt for each stream. I think that current enable/disable stream is more simple for this implementation. ~Gjorgji