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Fri, 05 Jun 2026 02:31:44 -0700 (PDT) X-Received: by 2002:a17:902:ea09:b0:2bc:8f9a:3642 with SMTP id d9443c01a7336-2c1e7e6eee0mr28230645ad.16.1780651904247; Fri, 05 Jun 2026 02:31:44 -0700 (PDT) Received: from [10.206.103.106] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c164fa3a5fsm91534805ad.36.2026.06.05.02.31.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 05 Jun 2026 02:31:43 -0700 (PDT) Message-ID: <59331aa7-8430-4754-861c-4ba6a4810ccd@oss.qualcomm.com> Date: Fri, 5 Jun 2026 15:01:37 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 2/2] phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver To: Dmitry Baryshkov , Vijay Kumar Tumati Cc: Bryan O'Donoghue , Vladimir Zapolskiy , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Bryan O'Donoghue , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260523-x1e-csi2-phy-v8-0-a85668459521@linaro.org> <20260523-x1e-csi2-phy-v8-2-a85668459521@linaro.org> <54904b61-222d-4600-ad4c-c03a9952d337@linaro.org> <8eb709ce-3469-4303-9c3d-8d1a221cb8de@linaro.org> Content-Language: en-US From: Nihal Kumar Gupta In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: ySOrJRLwMd0Krt59RoTcXOtc5ydxpCcT X-Proofpoint-ORIG-GUID: ySOrJRLwMd0Krt59RoTcXOtc5ydxpCcT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA1MDA5MiBTYWx0ZWRfX16qkrBKhhgSK FXyx0KGS7kz2N1Q8RRBwY6ZL7HcEWvc1xgIQ84tMPbFr3jgEx3kx4rG7yEqke9E8k3TuaxmZ5cj YMRVOXQDU8fcyETzB4QDzXW2+EwLxwd6feFYhKCqEWjjxxKiiDmKL4L0qzlmWIK/B/vPL+QkUG8 mYCyqwjcnRwy3HgVjkdDItoSD5RiX2maE/uV19UMzR9/s/4tV9DcSokblaU0qaS7vNHzD6EBXuY o7PgOC95LoBoAFv6CC8qQzvbTMW0oOHeO2B5B4OIHPPJyCjFTW0oPbVsxGH6e/tEQQGEvUl+o3x t5THF4adNqcQdh0gNIraQPqzYU/A4UN2FzwJhesLLgvaLmBKM7DZuHYnsrm3xPei6JQKXenmLCx 0t9shSLkLTG7CEieA9iE6tRDvztFUpEJgGMy1Asy5zixYj8eEw/V1wJPYgCtIQCbMccQU+tOQhz pMHRT2dNE8ty6sH1TGw== X-Authority-Analysis: v=2.4 cv=H9jrBeYi c=1 sm=1 tr=0 ts=6a229782 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=f6Fr6PdTwcyk7UrtzrMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-05_01,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 adultscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606050092 On 04-06-2026 03:44, Dmitry Baryshkov wrote: > On Wed, Jun 03, 2026 at 02:37:48PM -0700, Vijay Kumar Tumati wrote: >> >> >> On 6/3/2026 5:57 AM, Bryan O'Donoghue wrote: >>> On 03/06/2026 13:40, Dmitry Baryshkov wrote: >>>>> Are you sure about that ? >>>> Yes. >>>> >>>>> ipcat I thought designated lane 7 specifically as clk-lane i.e. named it >>>>> CLK_LN of some description. >>>> Split configurations explicitly use other lanes for clocks. E.g. check >>>> the RB5 Navigation schematics, CAM0B connector. >>> >>> Can you please check: >>> >>> CSI_3PHASE_COMMON.CSI_COMMON_CTRL5 >>> >>> 0 LN0_PWRDN_B Lane 0 >>> ... >>> 7 LNCK_PWRDN_B Clock Lane >>> >>> ... just a badly name field >>> >>> CSI_2PHASE_CTRL10 >>> >>> Bit[2] = IS_CLKLANE >>> >>> Right so CSI_2PHASE_CTRL10 controls lane mode, indeed. Thanks for checking. >> I can check this with the HW team. Although the SWI has this knob, there may >> be some limitations to use any lane as the clk lane. AFAIK, only two >> specific lanes are clk capable in DPHY mode.> > > Having clock-names property doesn't mean that all values are valid. > CSI_COMMON_CTRL5 is a physical lane power-up bitmap: - Bits [0,2,4,6] → D-PHY data lanes(LN0, LN2, LN4, LN6) - Bits [1,3,5] → C-PHY trio lanes(LN1, LN3, LN5) - Bit [7] → D-PHY clock lane(LNCK) dedicated clock enable In combo mode, only LN6 can be configurable as a clock lane. The lane-enable computation in phy_qcom_mipi_csi2_lanes_enable() uses BIT(data[i].pos) directly, assuming physical bit positions <0 2 4 6>, but the DT [1] uses conventional indices <0 1 2 3>, producing 0x8F instead of the correct 0xD5. This goes unnoticed because the wrong value is immediately overwritten by the hardcoded 0xD5 in lane_regs_x1e80100, making the dynamic computation effectively dead. Could you please fix the driver to map logical lane indices, consistent with the gen2 camss convention. [1] https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi-v3-5-1d5a9306116a@linaro.org Regards, Nihal