From: David Laight <David.Laight@ACULAB.COM>
To: 'Alexander Graf' <graf@amazon.com>,
'Thomas Gleixner' <tglx@linutronix.de>, 'X86 ML' <x86@kernel.org>
Cc: 'Andy Lutomirski' <luto@kernel.org>,
'LKML' <linux-kernel@vger.kernel.org>,
'Andrew Cooper' <andrew.cooper3@citrix.com>,
"'Paul E. McKenney'" <paulmck@kernel.org>,
'Alexandre Chartre' <alexandre.chartre@oracle.com>,
'Frederic Weisbecker' <frederic@kernel.org>,
'Paolo Bonzini' <pbonzini@redhat.com>,
'Sean Christopherson' <sean.j.christopherson@intel.com>,
'Masami Hiramatsu' <mhiramat@kernel.org>,
'Petr Mladek' <pmladek@suse.com>,
'Steven Rostedt' <rostedt@goodmis.org>,
'Joel Fernandes' <joel@joelfernandes.org>,
'Boris Ostrovsky' <boris.ostrovsky@oracle.com>,
'Juergen Gross' <jgross@suse.com>,
"'Mathieu Desnoyers'" <mathieu.desnoyers@efficios.com>,
'Josh Poimboeuf' <jpoimboe@redhat.com>,
'Will Deacon' <will@kernel.org>,
'Tom Lendacky' <thomas.lendacky@amd.com>,
'Wei Liu' <wei.liu@kernel.org>,
'Michael Kelley' <mikelley@microsoft.com>,
'Jason Chen CJ' <jason.cj.chen@intel.com>,
"'Zhao Yakui'" <yakui.zhao@intel.com>,
"'Peter Zijlstra (Intel)'" <peterz@infradead.org>,
'Avi Kivity' <avi@scylladb.com>,
"'Herrenschmidt, Benjamin'" <benh@amazon.com>,
"'robketr@amazon.de'" <robketr@amazon.de>,
"'amos@scylladb.com'" <amos@scylladb.com>,
'Brian Gerst' <brgerst@gmail.com>,
"'stable@vger.kernel.org'" <stable@vger.kernel.org>,
'Alex bykov' <alex.bykov@scylladb.com>
Subject: RE: x86/irq: Unbreak interrupt affinity setting
Date: Thu, 27 Aug 2020 08:31:28 +0000 [thread overview]
Message-ID: <5943d64220ee457b82f9a61fe17318e9@AcuMS.aculab.com> (raw)
In-Reply-To: <014fd671-73c1-97f3-cc92-73c2cf9576af@amazon.com>
From: Alexander Graf
> Sent: 26 August 2020 23:53
>
> On 26.08.20 23:47, David Laight wrote:
> >
> > From: David Laight
> >> Sent: 26 August 2020 22:37
> >>
> >> From: Thomas Gleixner
> >>> Sent: 26 August 2020 21:22
> >> ...
> >>> Moving interrupts on x86 happens in several steps. A new vector on a
> >>> different CPU is allocated and the relevant interrupt source is
> >>> reprogrammed to that. But that's racy and there might be an interrupt
> >>> already in flight to the old vector. So the old vector is preserved until
> >>> the first interrupt arrives on the new vector and the new target CPU. Once
> >>> that happens the old vector is cleaned up, but this cleanup still depends
> >>> on the vector number being stored in pt_regs::orig_ax, which is now -1.
> >>
> >> I suspect that it is much more 'racy' than that for PCI-X interrupts.
> >> On the hardware side there is an interrupt disable bit, and address
> >> and a value.
> >> To raise an interrupt the hardware must write the value to the address.
> >>
> >> If the cpu needs to move an interrupt both the address and value
> >> need changing, but the cpu wont write the address and value using
> >> the same TLP, so the hardware could potentially write a value to
> >> the wrong address.
> >> Worse than that, the hardware could easily only look at the address
> >> and value in the clocks after checking the interrupt is enabled.
> >> So masking the interrupt immediately prior to changing the vector
> >> info may not be enough.
> >>
> >> It is likely that a read-back of the mask before updating the vector
> >> is enough.
> >
> > But not enough to assume you won't receive an interrupt after reading
> > back that interrupts are masked.
> >
> > (I've implemented the hardware side for an fpga ...)
>
> Do we actually care in this context? All we want to know here is whether
> a device (or irqchip in between) has actually noticed that it should
> post to a new vector. If we get interrupts on random other vectors in
> between, they would simply show up as spurious, no?
>
> So I don't quite see where this patch makes the situation any worse than
> before.
Oh, it won't make it any worse.
It just might be rather worse than anyone imagined.
David
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next prev parent reply other threads:[~2020-08-27 8:31 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-26 11:53 [PATCH] x86/irq: Preserve vector in orig_ax for APIC code Alexander Graf
2020-08-26 13:22 ` Josh Poimboeuf
2020-08-26 13:51 ` Alexander Graf
2020-08-26 14:27 ` Thomas Gleixner
2020-08-26 16:13 ` Andy Lutomirski
2020-08-26 17:47 ` Thomas Gleixner
2020-08-26 18:00 ` Andy Lutomirski
2020-08-26 18:22 ` Graf (AWS), Alexander
2020-08-26 16:33 ` Alexander Graf
2020-08-26 18:30 ` Thomas Gleixner
2020-08-26 18:53 ` Thomas Gleixner
2020-08-26 20:09 ` Alexander Graf
2020-08-26 20:21 ` x86/irq: Unbreak interrupt affinity setting Thomas Gleixner
2020-08-26 21:37 ` David Laight
2020-08-26 21:47 ` David Laight
2020-08-26 22:52 ` Alexander Graf
2020-08-27 8:31 ` David Laight [this message]
2020-08-26 22:07 ` Thomas Gleixner
2020-08-27 8:28 ` David Laight
2020-08-27 7:32 ` [tip: x86/urgent] " tip-bot2 for Thomas Gleixner
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