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([2a00:f41:c03:9198:7df:6a16:3e8e:ed7b]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d30534e35sm4701537a12.62.2024.06.24.06.53.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Jun 2024 06:53:52 -0700 (PDT) Message-ID: <5947559d-30dd-4da1-93cc-a15dc65cb77d@linaro.org> Date: Mon, 24 Jun 2024 15:53:48 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/3] drm/msm/adreno: Add support for X185 GPU To: Akhil P Oommen , freedreno , dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Rob Clark , Bjorn Andersson Cc: Abhinav Kumar , Daniel Vetter , David Airlie , Dmitry Baryshkov , Marijn Suijten , Sean Paul , linux-kernel@vger.kernel.org References: <20240623110753.141400-1-quic_akhilpo@quicinc.com> <20240623110753.141400-3-quic_akhilpo@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20240623110753.141400-3-quic_akhilpo@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/23/24 13:06, Akhil P Oommen wrote: > Add support in drm/msm driver for the Adreno X185 gpu found in > Snapdragon X1 Elite chipset. > > Signed-off-by: Akhil P Oommen > --- > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++---- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---- > drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > 4 files changed, 36 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 0e3dfd4c2bc8..168a4bddfaf2 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) > */ > gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); > > + if (adreno_is_x185(adreno_gpu)) { > + chipid = 0x7050001; What's wrong with using the logic below? > /* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */ > - if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > + } else if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */ > chipid = FIELD_PREP(GENMASK(31, 24), 0x7); > > @@ -1329,9 +1331,18 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, > if (!pri_count) > return -EINVAL; > > - sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > - if (IS_ERR(sec)) > - return PTR_ERR(sec); > + /* > + * Some targets have a separate gfx mxc rail. So try to read that first and then fall back > + * to regular mx rail if it is missing > + */ > + sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); > + if (PTR_ERR_OR_ZERO(sec) == -EPROBE_DEFER) { > + return -EPROBE_DEFER; > + } else if (IS_ERR(sec)) { > + sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > + if (IS_ERR(sec)) > + return PTR_ERR(sec); > + } I assume GMXC would always be used if present, although please use the approach Dmitry suggested The rest looks good! Konrad