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[178.79.73.218]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429dc1f5be4sm5345170f8f.31.2025.11.04.08.50.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Nov 2025 08:50:06 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: wens@kernel.org Cc: mripard@kernel.org, maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, samuel@sholland.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 26/30] drm/sun4i: mixer: Add quirk for number of VI scalers Date: Tue, 04 Nov 2025 17:50:04 +0100 Message-ID: <5959058.DvuYhMxLoT@jernej-laptop> In-Reply-To: References: <20251012192330.6903-1-jernej.skrabec@gmail.com> <20251012192330.6903-27-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Hi Chen-Yu, Dne ponedeljek, 3. november 2025 ob 18:11:07 Srednjeevropski standardni =C4= =8Das je Chen-Yu Tsai napisal(a): > On Mon, Oct 13, 2025 at 3:24=E2=80=AFAM Jernej Skrabec wrote: > > > > On DE2 and DE3, UI scalers are located right after VI scalers. So in > > order to calculate proper UI scaler base address, number of VI scalers > > must be known. In practice, it is same as number of VI channels, but it > > doesn't need to be. > > > > Let's make a quirk for this number. Code for configuring channels and > > associated functions won't have access to vi_num quirk anymore after > > rework for independent planes. > > > > Signed-off-by: Jernej Skrabec > > --- > > drivers/gpu/drm/sun4i/sun8i_mixer.c | 11 +++++++++++ > > drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 ++ > > drivers/gpu/drm/sun4i/sun8i_ui_scaler.c | 10 +++++----- > > 3 files changed, 18 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4= i/sun8i_mixer.c > > index 78bbfbe62833..f9131396f22f 100644 > > --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c > > +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c > > @@ -708,6 +708,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixe= r0_cfg =3D { > > .scaler_mask =3D 0xf, > > .scanline_yuv =3D 2048, > > .de2_fcc_alpha =3D 1, > > + .vi_scaler_num =3D 1, > > .ui_num =3D 3, > > .vi_num =3D 1, > > }; > > @@ -718,6 +719,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixe= r1_cfg =3D { > > .scaler_mask =3D 0x3, > > .scanline_yuv =3D 2048, > > .de2_fcc_alpha =3D 1, > > + .vi_scaler_num =3D 1, > > .ui_num =3D 1, > > .vi_num =3D 1, > > }; > > @@ -729,6 +731,7 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0= _cfg =3D { > > .scaler_mask =3D 0xf, > > .scanline_yuv =3D 2048, > > .de2_fcc_alpha =3D 1, > > + .vi_scaler_num =3D 1, > > .ui_num =3D 3, > > .vi_num =3D 1, > > }; > > @@ -740,6 +743,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer= 0_cfg =3D { > > .scaler_mask =3D 0xf, > > .scanline_yuv =3D 2048, > > .de2_fcc_alpha =3D 1, > > + .vi_scaler_num =3D 1, > > .ui_num =3D 3, > > .vi_num =3D 1, > > }; > > @@ -751,6 +755,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer= 1_cfg =3D { > > .scaler_mask =3D 0x3, > > .scanline_yuv =3D 2048, > > .de2_fcc_alpha =3D 1, > > + .vi_scaler_num =3D 1, > > .ui_num =3D 1, > > .vi_num =3D 1, > > }; > > @@ -761,6 +766,7 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer= _cfg =3D { > > .ui_num =3D 1, > > .scaler_mask =3D 0x3, > > .scanline_yuv =3D 2048, > > + .vi_scaler_num =3D 2, > > .ccsc =3D CCSC_MIXER0_LAYOUT, > > .mod_rate =3D 150000000, > > }; > > @@ -772,6 +778,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer= 0_cfg =3D { > > .scaler_mask =3D 0x3, > > .scanline_yuv =3D 2048, > > .de2_fcc_alpha =3D 1, > > + .vi_scaler_num =3D 1, > > .ui_num =3D 1, > > .vi_num =3D 1, > > }; > > @@ -783,6 +790,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer= 1_cfg =3D { > > .scaler_mask =3D 0x1, > > .scanline_yuv =3D 1024, > > .de2_fcc_alpha =3D 1, > > + .vi_scaler_num =3D 1, > > .ui_num =3D 0, > > .vi_num =3D 1, > > }; > > @@ -794,6 +802,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixe= r0_cfg =3D { > > .scaler_mask =3D 0xf, > > .scanline_yuv =3D 4096, > > .de2_fcc_alpha =3D 1, > > + .vi_scaler_num =3D 1, > > .ui_num =3D 3, > > .vi_num =3D 1, > > }; > > @@ -805,6 +814,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixe= r1_cfg =3D { > > .scaler_mask =3D 0x3, > > .scanline_yuv =3D 2048, > > .de2_fcc_alpha =3D 1, > > + .vi_scaler_num =3D 1, > > .ui_num =3D 1, > > .vi_num =3D 1, > > }; > > @@ -814,6 +824,7 @@ static const struct sun8i_mixer_cfg sun50i_h6_mixer= 0_cfg =3D { > > .mod_rate =3D 600000000, > > .scaler_mask =3D 0xf, > > .scanline_yuv =3D 4096, > > + .vi_scaler_num =3D 1, > > .ui_num =3D 3, > > .vi_num =3D 1, > > }; > > diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4= i/sun8i_mixer.h > > index def07afd37e1..40b800022237 100644 > > --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h > > +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h > > @@ -178,6 +178,7 @@ enum sun8i_mixer_type { > > * @scaline_yuv: size of a scanline for VI scaler for YUV formats. > > * @de2_fcc_alpha: use FCC for missing DE2 VI alpha capability > > * Most DE2 cores has FCC. If number of VI planes is one, enable t= his. > > + * @vi_scaler_num: Number of VI scalers. Used on DE2 and DE3. > > * @map: channel map for DE variants processing YUV separately (DE33) > > */ > > struct sun8i_mixer_cfg { > > @@ -189,6 +190,7 @@ struct sun8i_mixer_cfg { > > unsigned int de_type; > > unsigned int scanline_yuv; > > unsigned int de2_fcc_alpha : 1; > > + unsigned int vi_scaler_num; >=20 > This could be a smaller type. Please do a sweep of the struct after the > refactoring is done and see if any of the types could be shrunk. A lot of things can be stored in smaller type. However, making things small= er may be contraproductive. Structs are usually aligned for performance reason= s, so it won't save any memory and accessing them will use extra asm instructi= ons for zeroing out parts of CPU registers since registers are larger than used data type. >=20 > And just a nitpick, but I would probably insert it above scaler_mask. >=20 Will do. >=20 > Reviewed-by: Chen-Yu Tsai >=20 Thanks. Best regards, Jernej