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X-CSE-ConnectionGUID: misd28V1TBK0mVZX/n4euA== X-CSE-MsgGUID: Q4MOB+ZJR8yuWyxmt393aA== X-IronPort-AV: E=McAfee;i="6700,10204,11410"; a="50619942" X-IronPort-AV: E=Sophos;i="6.15,229,1739865600"; d="scan'208";a="50619942" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2025 16:02:11 -0700 X-CSE-ConnectionGUID: 930LvW+rQ96x8ogVNgeKcA== X-CSE-MsgGUID: DMPzTLypRp+ab+28XKiAig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,229,1739865600"; d="scan'208";a="132798875" Received: from spandruv-desk1.amr.corp.intel.com ([10.125.111.93]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2025 16:02:10 -0700 Message-ID: <595bce6203d6d8951e312064bd5a8ba14c1fe141.camel@linux.intel.com> Subject: Re: [PATCH] Handle Ice Lake MONITOR erratum From: srinivas pandruvada To: Dave Hansen , linux-kernel@vger.kernel.org Cc: x86@kernel.org, andrew.cooper3@citrix.com, Len Brown , Peter Zijlstra , "Rafael J.Wysocki" , stable@vger.kernel.org Date: Mon, 21 Apr 2025 16:02:10 -0700 In-Reply-To: <20250421192205.7CC1A7D9@davehans-spike.ostc.intel.com> References: <20250421192205.7CC1A7D9@davehans-spike.ostc.intel.com> Autocrypt: addr=srinivas.pandruvada@linux.intel.com; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 (3.52.4-2.fc40) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Mon, 2025-04-21 at 12:22 -0700, Dave Hansen wrote: >=20 > From: Dave Hansen >=20 > Andrew Cooper reported some boot issues on Ice Lake servers when > running Xen that he tracked down to MWAIT not waking up. Do the safe > thing and consider them buggy since there's a published erratum. > Note: I've seen no reports of this occurring on Linux. >=20 > Add Ice Lake servers to the list of shaky MONITOR implementations > with > no workaround available. Also, before the if() gets too unwieldy, > move > it over to a x86_cpu_id array. Additionally, add a comment to the > X86_BUG_MONITOR consumption site to make it clear how and why > affected > CPUs get IPIs to wake them up. >=20 > There is no equivalent erratum for the "Xeon D" Ice Lakes so > INTEL_ICELAKE_D is not affected. >=20 > The erratum is called ICX143 in the "3rd Gen Intel Xeon Scalable > Processors, Codename Ice Lake Specification Update". It is Intel > document 637780, currently available here: >=20 > https://cdrdv2.intel.com/v1/dl/getContent/637780 >=20 > Signed-off-by: Dave Hansen > Cc: Andrew Cooper > Cc: Rafael J. Wysocki > Cc: Len Brown > Cc: Srinivas Pandruvada > Cc: Peter Zijlstra > Cc: stable@vger.kernel.org >=20 Reviewed-by: Srinivas Pandruvada Thanks, Srinivas > --- >=20 > =C2=A0b/arch/x86/include/asm/mwait.h |=C2=A0=C2=A0=C2=A0 3 +++ > =C2=A0b/arch/x86/kernel/cpu/intel.c=C2=A0 |=C2=A0=C2=A0 17 ++++++++++++++= --- > =C2=A02 files changed, 17 insertions(+), 3 deletions(-) >=20 > diff -puN arch/x86/kernel/cpu/intel.c~ICX-MONITOR-bug > arch/x86/kernel/cpu/intel.c > --- a/arch/x86/kernel/cpu/intel.c~ICX-MONITOR-bug 2025-04-18 > 13:54:46.022590596 -0700 > +++ b/arch/x86/kernel/cpu/intel.c 2025-04-18 > 15:15:19.374365069 -0700 > @@ -513,6 +513,19 @@ static void init_intel_misc_features(str > =C2=A0} > =C2=A0 > =C2=A0/* > + * These CPUs have buggy MWAIT/MONITOR implementations that > + * usually manifest as hangs or stalls at boot. > + */ > +#define MWAIT_VFM(_vfm) \ > + X86_MATCH_VFM_FEATURE(_vfm, X86_FEATURE_MWAIT, 0) > +static const struct x86_cpu_id monitor_bug_list[] =3D { > + MWAIT_VFM(INTEL_ATOM_GOLDMONT), > + MWAIT_VFM(INTEL_LUNARLAKE_M), > + MWAIT_VFM(INTEL_ICELAKE_X), /* Erratum ICX143 */ > + {}, > +}; > + > +/* > =C2=A0 * This is a list of Intel CPUs that are known to suffer from > downclocking when > =C2=A0 * ZMM registers (512-bit vectors) are used.=C2=A0 On these CPUs, w= hen > the kernel > =C2=A0 * executes SIMD-optimized code such as cryptography functions or > CRCs, it > @@ -565,9 +578,7 @@ static void init_intel(struct cpuinfo_x8 > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0 c->x86_vfm =3D=3D INTEL_WESTMERE_EX)) > =C2=A0 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); > =C2=A0 > - if (boot_cpu_has(X86_FEATURE_MWAIT) && > - =C2=A0=C2=A0=C2=A0 (c->x86_vfm =3D=3D INTEL_ATOM_GOLDMONT || > - =C2=A0=C2=A0=C2=A0=C2=A0 c->x86_vfm =3D=3D INTEL_LUNARLAKE_M)) > + if (x86_match_cpu(monitor_bug_list)) > =C2=A0 set_cpu_bug(c, X86_BUG_MONITOR); > =C2=A0 > =C2=A0#ifdef CONFIG_X86_64 > diff -puN arch/x86/include/asm/mwait.h~ICX-MONITOR-bug > arch/x86/include/asm/mwait.h > --- a/arch/x86/include/asm/mwait.h~ICX-MONITOR-bug 2025-04-18 > 15:17:18.353749634 -0700 > +++ b/arch/x86/include/asm/mwait.h 2025-04-18 > 15:20:06.037927656 -0700 > @@ -110,6 +110,9 @@ static __always_inline void __sti_mwait( > =C2=A0 * through MWAIT. Whenever someone changes need_resched, we would b= e > woken > =C2=A0 * up from MWAIT (without an IPI). > =C2=A0 * > + * Buggy (X86_BUG_MONITOR) CPUs will never set the polling bit and > will > + * always be sent IPIs. > + * > =C2=A0 * New with Core Duo processors, MWAIT can take some hints based on > CPU > =C2=A0 * capability. > =C2=A0 */ > _