From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751347AbdIOHTY (ORCPT ); Fri, 15 Sep 2017 03:19:24 -0400 Received: from bizsmtp.net4india.com ([118.67.236.10]:43409 "EHLO smtp.bizmail.net4india.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750865AbdIOHTW (ORCPT ); Fri, 15 Sep 2017 03:19:22 -0400 Date: Fri, 15 Sep 2017 12:46:25 +0530 (IST) From: Fahad Kunnathadi To: Andrew Lunn Cc: f fainelli , netdev@vger.kernel.org, Michal Simek , linux-kernel@vger.kernel.org, soren brinkmann , linux-arm-kernel@lists.infradead.org Message-ID: <597180344.2790975.1505459785154.JavaMail.zimbra@dexceldesigns.com> In-Reply-To: <20170914143454.GB27601@lunn.ch> References: <1505373391-18697-1-git-send-email-fahad.kunnathadi@dexceldesigns.com> <20170914143454.GB27601@lunn.ch> Subject: Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter speed register. MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Originating-IP: [192.168.0.222] X-Mailer: Zimbra 8.7.0_GA_1659 (ZimbraWebClient - FF49 (Linux)/8.7.0_GA_1659) Thread-Topic: Fix mask value write on gmii2rgmii converter speed register. Thread-Index: n+jEvAnBIiuSmYjoXO4VFful/A05mQ== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Andrew, Thank you for review and comments. I will review this driver code with any review comments before, and update you if I could find any.. Best Regards Fahad K ----- Original Message ----- From: "Andrew Lunn" To: "Fahad Kunnathadi" Cc: "f fainelli" , netdev@vger.kernel.org, "Michal Simek" , linux-kernel@vger.kernel.org, "soren brinkmann" , linux-arm-kernel@lists.infradead.org Sent: Thursday, September 14, 2017 8:04:54 PM Subject: Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter speed register. On Thu, Sep 14, 2017 at 12:46:31PM +0530, Fahad Kunnathadi wrote: > To clear Speed Selection in MDIO control register(0x10), > ie, clear bits 6 and 13 to zero while keeping other bits same. > Before AND operation,The Mask value has to be perform with bitwise NOT > operation (ie, ~ operator) > > This patch clears current speed selection before writing the > new speed settings to gmii2rgmii converter Hi Fahad I expect you will find other issues with this driver. I pointed some out at the time it is submitted, but the developers went quiet as soon as it was accepted. Anyway, please ensure David Miller gets a copy. The subject line should be: [PATCH net] net: phy: Fix mask value write on gmii2rgmii converter speed register. and include a fixes tag: Fixes: f411a6160bd4 ("net: phy: Add gmiitorgmii converter support") Reviewed-by: Andrew Lunn Andrew