From: Steven Newbury <s_j_newbury@yahoo.co.uk>
To: saeed bishara <saeed.bishara@gmail.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.arm.linux.org.uk
Subject: Re: cache coherecy when working with cpu dcache write allocate
Date: Tue, 6 Feb 2007 20:55:03 +0000 (GMT) [thread overview]
Message-ID: <598785.29036.qm@web25003.mail.ukl.yahoo.com> (raw)
In-Reply-To: <c70ff3ad0702061031i6face64ai946d6893b960645b@mail.gmail.com>
--- saeed bishara <saeed.bishara@gmail.com> wrote:
> Hi,
> I came across data corruption problem when using xfs, my system is
> arm 926, the data cache is virtually tagged and virtually indexed and
> with no hw cache coherency. my CPU features the data cache write
> allocate-> when doing store, the cache line of the destination address
> is loaded to data cache.
> when enabling the write allocate, I got data corruption with the
> xfs. the scenario is that the xfs allocates large buffer (for reading
> the log records) using vmalloc, and the low level driver (raid) copies
> the data to the bio vectors using the linear address, since the write
> allocate is enabled, the correct data remains on the data cache with
> the linear address tag, when the IO completes, the xfs access the data
> with using the vmalloc virtual address, which is different than the
> kernel linear address, thus it will get a stale data!.
>
> how should I fix this problem? I thought that only the
> copy/clean_user_pages() functions should be aware to the write
> allocate.
I wonder if I'm seeing this with reiser4 on pxa27x as well???
Steve
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prev parent reply other threads:[~2007-02-06 21:01 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-02-06 18:31 saeed bishara
2007-02-06 20:55 ` Steven Newbury [this message]
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