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All rights reserved >>>> +%YAML 1.2 >>>> +--- >>>> +$id:http://devicetree.org/schemas/media/amlogic,s4-vcodec-dec.yaml# >>>> +$schema:http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Amlogic Video Decode Accelerator >>>> + >>>> +maintainers: >>>> + - Zhentao Guo >>>> + >>>> +description: >>>> + The Video Decoder Accelerator present on Amlogic SOCs. >>>> + It supports stateless h264 decoding. >>>> + >>>> +properties: >>>> + compatible: >>>> + const: amlogic,s4-vcodec-dec >>> Why do you repeat "dec" twice? codec means decoder, so what is the last >>> "dec" about? >> In fact, codec means encoder+decoder, and dec is short for decoder. > Yes, that's what I meant, so why do you repeat decoder? Since this patch only involves the decoder, we want to highlight the decoder. We’ll consider a new node name, the current one is indeed redundant. >>>> + >>>> + reg: >>>> + maxItems: 2 >>>> + >>>> + reg-names: >>>> + items: >>>> + - const: dos >>>> + - const: dmc >>>> + >>>> + interrupts: >>>> + maxItems: 3 >>>> + >>>> + clocks: >>>> + maxItems: 3 >>>> + >>>> + clock-names: >>>> + items: >>>> + - const: vdec >>>> + - const: clk_vdec_mux >>>> + - const: clk_hevcf_mux >>> Name them based on their role/name in this device. Why this device would >>> care that it receives a mux? Not a div? or not a gate? >> Ok, previously we overlooked this. We will improve it in the next version. >>>> + >>>> + power-domains: >>>> + maxItems: 2 >>>> + >>>> + power-domain-names: >>>> + items: >>>> + - const: vdec >>>> + - const: hevc >>>> + >>>> + resets: >>>> + maxItems: 1 >>>> + >>>> + amlogic,canvas: >>>> + description: should point to a canvas provider node >>> Why? What for? >>> >>> What is canvas provider? >> The canvas provider is: drivers/soc/amlogic/meson-canvas.c > What is this "canvas" device. You can think of canvas as the agent through which the decoder hardware accesses DDR. >> In short, canvas is a hardware IP inside the Amlogic SoC. The decoder IP >> needs to access DDR through canvas IP, so we need to reference the > Why decoder cannot access DDR directly? The internal topology of the S4 chip is designed this way, we don't know why our VLSI colleauges designed like this. But similar designs have been removed in subsequent chips, eliminating the need to rely on a common hardware IP. > Best regards, > Krzysztof BRs Zhentao