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Tue, 25 Aug 2020 11:08:20 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 87B1842045; Tue, 25 Aug 2020 11:08:18 +0000 (GMT) Received: from [9.199.33.167] (unknown [9.199.33.167]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 25 Aug 2020 11:08:18 +0000 (GMT) Subject: Re: [PATCH v5 4/8] powerpc/watchpoint: Move DAWR detection logic outside of hw_breakpoint.c To: Christophe Leroy , christophe.leroy@c-s.fr Cc: mpe@ellerman.id.au, mikey@neuling.org, paulus@samba.org, naveen.n.rao@linux.vnet.ibm.com, pedromfc@linux.ibm.com, rogealve@linux.ibm.com, jniethe5@gmail.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Ravi Bangoria References: <20200825043617.1073634-1-ravi.bangoria@linux.ibm.com> <20200825043617.1073634-5-ravi.bangoria@linux.ibm.com> <0a73280b-c231-a7bb-18d9-abf2a37ba24b@csgroup.eu> From: Ravi Bangoria Message-ID: <59ac33ed-4ed3-2c92-7b0b-1d14abf7186b@linux.ibm.com> Date: Tue, 25 Aug 2020 16:38:17 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <0a73280b-c231-a7bb-18d9-abf2a37ba24b@csgroup.eu> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-08-25_02:2020-08-25,2020-08-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 suspectscore=0 malwarescore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008250079 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Christophe, >> +static int cache_op_size(void) >> +{ >> +#ifdef __powerpc64__ >> +    return ppc64_caches.l1d.block_size; >> +#else >> +    return L1_CACHE_BYTES; >> +#endif >> +} > > You've got l1_dcache_bytes() in arch/powerpc/include/asm/cache.h to do that. > >> + >> +void wp_get_instr_detail(struct pt_regs *regs, struct ppc_inst *instr, >> +             int *type, int *size, unsigned long *ea) >> +{ >> +    struct instruction_op op; >> + >> +    if (__get_user_instr_inatomic(*instr, (void __user *)regs->nip)) >> +        return; >> + >> +    analyse_instr(&op, regs, *instr); >> +    *type = GETTYPE(op.type); >> +    *ea = op.ea; >> +#ifdef __powerpc64__ >> +    if (!(regs->msr & MSR_64BIT)) >> +        *ea &= 0xffffffffUL; >> +#endif > > This #ifdef is unneeded, it should build fine on a 32 bits too. This patch is just a code movement from one file to another. I don't really change the logic. Would you mind if I do a separate patch for these changes (not a part of this series)? Thanks for review, Ravi