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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aff0d9b1b53sm2408307666b.96.2025.09.08.08.38.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Sep 2025 08:38:02 -0700 (PDT) Message-ID: <59ac7827-6258-4268-8b71-4cbcbad859db@oss.qualcomm.com> Date: Mon, 8 Sep 2025 17:37:59 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 07/16] drm/msm/adreno: Add fenced regwrite support To: Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Antonino Maniscalco , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20250908-ifpc-support-v2-0-631b1080bf91@oss.qualcomm.com> <20250908-ifpc-support-v2-7-631b1080bf91@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250908-ifpc-support-v2-7-631b1080bf91@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: EAq0FAuab9RB2wtJYNPq8RrsWv-fjcgH X-Proofpoint-GUID: EAq0FAuab9RB2wtJYNPq8RrsWv-fjcgH X-Authority-Analysis: v=2.4 cv=NdLm13D4 c=1 sm=1 tr=0 ts=68bef85d cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=sRrLox2IjJLVq2cxUxUA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA4MDA2NiBTYWx0ZWRfXyzmklhId7uVg 3PHNkPJGyeixxNueL/6KjXqtXP7f6Co10RfOjCIM2inyuenIdqt+PMec3aGd8PqzpYCWpByKHJu fX65XB5/nZRI2Ly8EcohVrJV3cil3GrMTLRaM6d1R1pjmGc1gQkQFhZuHq8LUmm4qhTx2JCM4hL LH598g3CQGgTW8kzNu2C1f8DtqjQyIXS5eCJBlrmkPU8eKzkGdffQVMvaH3Id1aAGzirVKrHMzI NLELFaS88H4VKTMyLRG2ZUZO01RlKMhQ6A6N6NCb/wmGAX1JkO6idvx/Sq0fEEHrAJ8b9ZivlrJ DajRHHqXOm0950ciADL2XhwGiM0pXkUJvITmjHo76nCSj11t0krD5gJHgcatruzXi7javEeISpq LUSOwLTJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_05,2025-09-08_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 adultscore=0 suspectscore=0 phishscore=0 clxscore=1015 impostorscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509080066 On 9/8/25 10:27 AM, Akhil P Oommen wrote: > There are some special registers which are accessible even when GX power > domain is collapsed during an IFPC sleep. Accessing these registers > wakes up GPU from power collapse and allow programming these registers > without additional handshake with GMU. This patch adds support for this > special register write sequence. > > Signed-off-by: Akhil P Oommen > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 80 ++++++++++++++++++++++++++++++- > drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + > drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 20 ++++---- > 3 files changed, 90 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 45dd5fd1c2bfcb0a01b71a326c7d95b0f9496d99..a63dad80ef461da45d5c41a042ed4f19d8282ef5 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -16,6 +16,84 @@ > > #define GPU_PAS_ID 13 > > +static bool fence_status_check(struct msm_gpu *gpu, u32 offset, u32 value, u32 status, u32 mask) > +{ > + /* Success if !writedropped0/1 */ > + if (!(status & mask)) > + return true; > + > + udelay(10); > + > + /* Try to update fenced register again */ > + gpu_write(gpu, offset, value); > + > + /* We can't do a posted write here because the power domain could be > + * in collapse state. So use the heaviest barrier instead > + */ > + mb(); > + return false; > +} > + > +static int fenced_write(struct a6xx_gpu *a6xx_gpu, u32 offset, u32 value, u32 mask) > +{ > + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; > + struct msm_gpu *gpu = &adreno_gpu->base; > + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; > + u32 status; > + > + gpu_write(gpu, offset, value); > + > + /* Nothing else to be done in the case of no-GMU */ > + if (adreno_has_gmu_wrapper(adreno_gpu)) > + return 0; > + > + /* We can't do a posted write here because the power domain could be > + * in collapse state. So use the heaviest barrier instead > + */ I'm not sure I follow - what's the relationship between the write being posted and the power domain being collapsed (i.e. the hw not being powered on)? Are you trying to get rid of the delay that could happen between this write leaving the CPU and arriving at the GPU (which would then be woken up), so that the 1ms poll below has greater chance to succeed because of how these "special registers" work? Konrad