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Tue, 03 Mar 2026 09:15:51 -0800 (PST) Message-ID: <59c3c6324ca971dc081624e0c31131b9e7dc9c63.camel@gmail.com> Subject: Re: [PATCH RFC 6/8] iio: frequency: ad9910: add RAM mode support From: Nuno =?ISO-8859-1?Q?S=E1?= To: Rodrigo Alencar <455.rodrigo.alencar@gmail.com>, Jonathan Cameron , Rodrigo Alencar via B4 Relay Cc: rodrigo.alencar@analog.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen , Michael Hennerich , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Date: Tue, 03 Mar 2026 17:16:35 +0000 In-Reply-To: <4rzqg6gax4r3symyoimekikz7p4pfwjzhfamjudk64f32675oj@nlrz53u56p55> References: <20260220-ad9910-iio-driver-v1-0-3b264aa48a10@analog.com> <20260220-ad9910-iio-driver-v1-6-3b264aa48a10@analog.com> <20260301133153.7f2f8501@jic23-huawei> <4rzqg6gax4r3symyoimekikz7p4pfwjzhfamjudk64f32675oj@nlrz53u56p55> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2026-03-03 at 15:32 +0000, Rodrigo Alencar wrote: > On 26/03/01 01:31PM, Jonathan Cameron wrote: > > On Fri, 20 Feb 2026 16:46:10 +0000 > > Rodrigo Alencar via B4 Relay wrote: > >=20 > > > From: Rodrigo Alencar > > >=20 > > > Add RAM channel with support for profile-based control. This includes= : > > > - RAM data loading via binary sysfs attribute (ram_data); > >=20 > > I'm not sure that's a long term viable path.=C2=A0 We either need > > to figure out how to do it as firmware file load, or via an output buff= er. >=20 > Could you develop on this? it is not viable because iio would drop that > support? using sysfs_create_bin_file() directly would be better? >=20 > > Firmware load would probably be too static and I'm not sure quite > > how we map these to IIO output buffers. >=20 > will investigate this buffer route. At this point, we can have multiple > buffers, right? I have the DMA engine buffer working with the parallel po= rt. >=20 > ...=20 In theory yes but we do have some issues with the implementation. I have so= me fixes but for code that, unfortunately, cannot land upstream anytime soon a= nd with no users, these fixes can be an hard sell. So if we go the multi buffer sup= port it could be a great opportunity for these. That said, the fixes are only meaningful if we do need to restrict channels= to a specific buffer. Not sure if that will be the case here. - Nuno S=C3=A1