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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1384b964862sm8982362c88.10.2026.06.14.18.18.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 14 Jun 2026 18:18:16 -0700 (PDT) Message-ID: <59dbf955-56d5-4d72-85ca-0ed8407de295@gmail.com> Date: Mon, 15 Jun 2026 09:18:12 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] dt-bindings: spi: nuvoton,ma35d1-qspi: Add Nuvoton MA35D1 QSPI To: Conor Dooley Cc: broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com References: <20260611091246.2070485-1-cwweng.linux@gmail.com> <20260611091246.2070485-2-cwweng.linux@gmail.com> <20260611-decoy-glamorous-81903a5fd1f9@spud> <0031379c-0cc3-40c8-8145-5b1991b42f05@gmail.com> <20260612-diagram-florist-01a0e8f923d8@spud> Content-Language: en-US From: Chi-Wen Weng In-Reply-To: <20260612-diagram-florist-01a0e8f923d8@spud> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Conor, Thanks for the clarification. I will make the driver read num-cs in v4 and fall back to the hardware default of 2 when the property is not present. I will also keep the binding default in sync with that behavior. Best regards, Chi-Wen Conor Dooley 於 2026/6/12 下午 11:48 寫道: > On Fri, Jun 12, 2026 at 08:33:01AM +0800, Chi-Wen Weng wrote: >> Hi Conor, >> >> Thanks for the review. >> >> I will add a default value for num-cs in v4: >> >>   num-cs: >>     maximum: 2 >>     default: 2 >> >> The controller has two native chip selects and the driver currently uses >> that hardware default. > The driver should handle the property and fall back to the default. > It's not complex to support, so surely there's no reason not to? > > Cheers, > Conor. > >> Best regards, >> Chi-Wen >> >> Conor Dooley 於 2026/6/12 上午 01:34 寫道: >>> On Thu, Jun 11, 2026 at 05:12:45PM +0800, Chi-Wen Weng wrote: >>>> From: Chi-Wen Weng >>>> >>>> Add a devicetree binding for the Quad SPI controller found in >>>> Nuvoton MA35D1 SoCs. >>>> >>>> The controller supports SPI memory devices such as SPI NOR and SPI NAND >>>> flashes. It has one register range, one clock input and one reset line, >>>> and supports up to two chip selects. >>>> >>>> Signed-off-by: Chi-Wen Weng >>>> --- >>>> .../bindings/spi/nuvoton,ma35d1-qspi.yaml | 62 +++++++++++++++++++ >>>> 1 file changed, 62 insertions(+) >>>> create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml >>>> >>>> diff --git a/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml >>>> new file mode 100644 >>>> index 000000000000..d3b36e612eb0 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml >>>> @@ -0,0 +1,62 @@ >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/spi/nuvoton,ma35d1-qspi.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Nuvoton MA35D1 Quad SPI Controller >>>> + >>>> +maintainers: >>>> + - Chi-Wen Weng >>>> + >>>> +allOf: >>>> + - $ref: /schemas/spi/spi-controller.yaml# >>>> + >>>> +properties: >>>> + compatible: >>>> + const: nuvoton,ma35d1-qspi >>>> + >>>> + reg: >>>> + maxItems: 1 >>>> + >>>> + interrupts: >>>> + maxItems: 1 >>>> + >>>> + clocks: >>>> + maxItems: 1 >>>> + >>>> + resets: >>>> + maxItems: 1 >>>> + >>>> + num-cs: >>>> + maximum: 2 >>> Missing a default of 2, unless you make the property required. >>> FWIW, your driver doesn't appear to read this value. >>> >>> pw-bot: changes-requested >>> >>> Cheers, >>> Conor. >>> >>>> + >>>> +required: >>>> + - compatible >>>> + - reg >>>> + - clocks >>>> + - resets >>>> + >>>> +unevaluatedProperties: false >>>> + >>>> +examples: >>>> + - | >>>> + #include >>>> + #include >>>> + #include >>>> + >>>> + soc { >>>> + #address-cells = <2>; >>>> + #size-cells = <2>; >>>> + >>>> + spi@40680000 { >>>> + compatible = "nuvoton,ma35d1-qspi"; >>>> + reg = <0 0x40680000 0 0x100>; >>>> + interrupts = ; >>>> + clocks = <&clk QSPI0_GATE>; >>>> + resets = <&sys MA35D1_RESET_QSPI0>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + }; >>>> + }; >>>> + >>>> -- >>>> 2.25.1 >>>>