From: Hal Feng <hal.feng@linux.starfivetech.com>
To: E Shattow <e@freeshell.de>, Conor Dooley <conor@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v1 2/5] riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz
Date: Tue, 14 Jan 2025 15:27:33 +0800 [thread overview]
Message-ID: <5F5ACE98B916A290+edc923d2-0ee8-4e41-8e69-f6603ef014fa@linux.starfivetech.com> (raw)
In-Reply-To: <20250102194530.418127-3-e@freeshell.de>
On 1/3/2025 3:45 AM, E Shattow wrote:
> Sync qspi flash setting to read-delay=2 and spi-max-frequency 100MHz for
> better compatibility with operating system and downstream boot loader SPL
> secondary program loader.
>
> Signed-off-by: E Shattow <e@freeshell.de>
> ---
> arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> index 55c6743100a7..651f9a602226 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> @@ -317,8 +317,8 @@ &qspi {
> nor_flash: flash@0 {
> compatible = "jedec,spi-nor";
> reg = <0>;
> - cdns,read-delay = <5>;
> - spi-max-frequency = <12000000>;
> + cdns,read-delay = <2>;
> + spi-max-frequency = <100000000>;
> cdns,tshsl-ns = <1>;
> cdns,tsd2d-ns = <1>;
> cdns,tchsh-ns = <1>;
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
next prev parent reply other threads:[~2025-01-14 7:27 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-02 19:45 [PATCH v1 0/5] riscv: dts: starfive: jh7110-common: Sync downstream U-Boot changes E Shattow
2025-01-02 19:45 ` [PATCH v1 1/5] riscv: dts: starfive: jh7110-common: replace syscrg clock assignments E Shattow
2025-01-04 18:33 ` Conor Dooley
2025-01-04 21:04 ` E Shattow
2025-01-06 20:08 ` Conor Dooley
2025-01-15 6:33 ` Hal Feng
2025-01-15 9:35 ` Conor Dooley
2025-01-24 10:46 ` E Shattow
2025-02-07 8:17 ` Hal Feng
2025-01-02 19:45 ` [PATCH v1 2/5] riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz E Shattow
2025-01-14 7:27 ` Hal Feng [this message]
2025-01-02 19:45 ` [PATCH v1 3/5] riscv: dts: starfive: jh7110-common: assign 24MHz clock-frequency to uart0 E Shattow
2025-01-02 19:45 ` [PATCH v1 4/5] riscv: dts: starfive: jh7110-common: add eeprom node to i2c5 E Shattow
2025-01-14 8:28 ` Hal Feng
2025-01-02 19:45 ` [PATCH v1 5/5] riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader E Shattow
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